Doherty Peak Amplifier Bias Control for High-Speed Signals
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Solution Overview
Problem
Existing Doherty amplifier circuits struggle to support high-speed communication due to inadequate control of bias circuits, leading to signal distortion and delayed response times.
Innovation Solution
A Doherty amplifier circuit design that includes a driver-stage peak amplifier with two amplifiers and a drive-level detection circuit to quickly adjust biases based on detected drive levels, allowing for high-frequency signal amplification without the need for an adder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an adder is used to combine detection signal and another signal for bias control, then the bias control can be implemented, but the control cannot follow the change speed of the output signal and large distortion occurs
Solution Approach 1:
The patent introduces a buffer circuit as an intermediary between the detection signal and the bias control circuit. This buffer circuit isolates the high-speed detection signal from the slower bias control circuit, allowing the bias control to respond quickly to signal changes without the distortion caused by direct adder combination. The buffer acts as a mediator that preserves signal integrity while enabling proper bias adjustment.
Solution Approach 2:
The patent segments the bias control function into separate circuits: a buffer circuit for signal isolation and a bias control circuit for actual bias adjustment. This segmentation allows each circuit to be optimized for its specific function - the buffer for high-speed signal handling and the bias control for precise bias management - thereby resolving the contradiction between control capability and response speed.
2Reliability
If conventional bias control is used in Doherty amplifier, then the amplifier can operate, but it cannot support high-speed communication due to delayed response times
Solution Approach 1:
The buffer circuit performs preliminary action by pre-processing the detection signal before it reaches the bias control circuit. This preliminary buffering action prepares the signal in advance, reducing the overall response time of the bias control system and enabling the amplifier to support high-speed communication while maintaining operational stability.
3Device complexity
If the peak amplifier bias is not quickly adjusted, then the circuit is simpler, but signal distortion increases and high-speed communication cannot be supported
Solution Approach 1:
The buffer circuit serves as a simple intermediary that enables fast bias adjustment without significantly increasing circuit complexity. By inserting this single buffer stage, the patent achieves both quick bias adjustment for high signal fidelity and maintains relatively simple circuit structure, resolving the contradiction between device complexity and signal quality.
Data Source
AI summary
A Doherty amplifier circuit capable of supporting high-speed communication is attained. The Doherty amplifier circuit includes a carrier amplifier that amplifies a first high frequency signal corresponding to an input high frequency signal, a driver-stage peak amplifier that amplifies a second high frequency signal having a predetermined phase relationship with a phase of the first high frequency signal, a power-stage peak amplifier that receives an outputted from the driver-stage peak amplifier, and a drive-level detection circuit that detects a drive level of the carrier amplifier. The driver-stage peak amplifier includes a first amplifier and a second amplifier. A bias based on a drive level signal indicating the drive level detected by the drive-level detection circuit is supplied to one of the first amplifier and the second amplifier. A bias corresponding to the input high frequency is supplied to the other one of the first amplifier and the second amplifier.