Doherty Amplifier Chip Layout for Isolation and Compact Packaging
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Solution Overview
Problem
Existing semiconductor devices, particularly Doherty amplifiers, face challenges in reducing size and minimizing signal interference between parallel amplifiers, which affects their efficiency and performance.
Innovation Solution
The semiconductor device configuration includes a first and second semiconductor chip with amplifiers, a passive element chip with matching and bias circuits, and bonding wires, where the distance between input pads is shorter than output pads, allowing for reduced size and improved signal isolation through strategic placement of matching and bias circuits and reference potential pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the distance between input pads and output pads is increased to accommodate matching circuits and bonding wires, then signal interference is reduced, but the overall device size increases
Solution Approach 1:
The patent arranges matching circuits and bonding wires in the vertical dimension (stacked configuration) rather than spreading them out horizontally. The passive element chip is positioned between input and output pads in the vertical direction, allowing matching circuits to be integrated on this intermediate chip, thereby reducing the horizontal footprint while maintaining adequate signal paths and isolation.
Solution Approach 2:
The patent integrates multiple functional elements into a nested structure where the passive element chip containing matching circuits is positioned between the input and output pads, effectively nesting the matching functionality within the existing device architecture. This nested arrangement allows matching circuits to be incorporated without significantly increasing the overall device envelope.
2Object-affected harmful factors
If matching circuits and bias circuits are integrated on a separate passive element chip, then signal isolation is improved, but device complexity increases
Solution Approach 1:
The patent segments the device into functional modules: active devices on semiconductor chips, passive matching circuits and bias circuits on a separate passive element chip, and interconnection via bonding wires. This segmentation isolates signal paths, improves matching performance, and allows independent optimization of active and passive components while maintaining manageable overall complexity.
Solution Approach 2:
The passive element chip serves multiple functions simultaneously: it provides matching circuits for impedance transformation, bias circuits for DC voltage generation, and physical spacing for signal isolation. This multi-functionality consolidates several necessary components into a single intermediate element, reducing overall device complexity while achieving multiple design objectives.
Data Source
AI summary
A semiconductor device includes a first semiconductor chip having a first amplifier and a first output pad, a second semiconductor chip having a second amplifier, a third semiconductor chip having a third amplifier and a second output pad, a fourth semiconductor chip having a fourth amplifier, a passive element chip including a first matching circuit connected between the first amplifier and the second amplifier, a second matching circuit connected between the third amplifier and the fourth amplifier, a first input pad electrically connected to the first output pad, and a second input pad electrically connected to the second output pad, wherein a distance between the first input pad and the second input pad in a second direction intersecting the first direction is shorter than a distance between the first output pad and the second output pad in the second direction.