Doherty Peak Amplifier Biasing for Synchronized Turn-On
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Solution Overview
Problem
In Doherty type power amplifier circuits, the transistors in the peak amplifier stages have timing delays in turning on, leading to reduced power efficiency and increased leakage current due to the need for shallow gate biases and complex bias control circuits, especially at higher frequencies.
Innovation Solution
A power amplifier circuit configuration with a current-reuse structure where transistors are connected in series, allowing independent biasing of each transistor stage, enabling synchronized turn-on times and reducing leakage current without the need for complex bias control circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If transistors in peak amplifier stages use shallow gate biases to accommodate timing delays, then timing flexibility is improved, but leakage current increases and power efficiency deteriorates
Solution Approach 1:
The peak amplifier is divided into multiple stages with independently biasable transistors. Each transistor stage can be independently controlled through separate bias circuits, allowing precise timing control without requiring shallow gate biases across all stages. This segmentation enables each stage to operate at optimal bias points, reducing leakage current while maintaining timing flexibility.
Solution Approach 2:
The bias circuits are designed to dynamically adjust gate biases based on operating conditions and timing requirements. Rather than using fixed shallow biases, the system can apply deeper biases when needed while maintaining proper turn-on timing through dynamic control, thereby reducing leakage current while preserving timing flexibility.
2Loss of time
If complex bias control circuits are used to synchronize transistor turn-on times, then timing precision is improved, but device complexity increases
Solution Approach 1:
The bias control is segmented into multiple independent bias circuits, each responsible for a specific transistor stage. This eliminates the need for a single complex centralized bias control circuit, as each simple independent circuit can be optimized for its specific stage without requiring coordination with other stages.
Solution Approach 2:
The independent bias circuits are designed to pre-establish appropriate gate biases for each transistor stage before signal amplification begins. By preparing the bias conditions in advance for each stage independently, the system achieves synchronized turn-on without requiring complex real-time coordination circuits.
3Power
If transistors are connected in parallel configuration, then current handling capability is improved, but timing synchronization becomes more difficult and leakage current increases
Solution Approach 1:
Instead of connecting transistors in parallel as conventionally done, the invention uses a series connection configuration for the transistor stages in the peak amplifier. This inversion of the traditional parallel architecture allows each transistor to handle current sequentially while maintaining precise timing control through independent biasing, thereby achieving current handling capability without the timing synchronization problems inherent in parallel configurations.
Data Source
AI summary
A power amplifier circuit is a Doherty type. A peak amplifier has a first transistor and a second transistor. A first source terminal is connected to a first constant potential line. A first drain terminal and a second source terminal are connected to a first node. A second drain terminal is connected to a second constant potential line having a higher potential than the first constant potential line. A first control terminal is connected to a first bias voltage application circuit, and an input signal is input to the first control terminal via a first alternating current coupling circuit. A second control terminal is connected to a second bias voltage application circuit and is connected to the first node via a second alternating current coupling circuit. The first node is connected to the first constant potential line via a third alternating current coupling circuit.