Doherty Amplifier Peak Lead Layout for Oscillation Suppression
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Solution Overview
Problem
GaN transistors with large gate peripheries face challenges such as low yield, unwanted oscillations, and push-pull type oscillations in Doherty amplifiers, particularly in high-power applications.
Innovation Solution
A Doherty amplifier design incorporating a slot in the peak output lead with a length corresponding to a fraction of the operational wavelength, dividing the lead into separate parts connected to individual transistors, and using transmission lines and resistors to suppress oscillations and improve stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a large gate periphery GaN transistor is used to deliver high power (700W+), then the power output is improved, but the manufacturing yield deteriorates and unwanted oscillations occur
Solution Approach 1:
The patent divides a single large gate periphery transistor into multiple smaller transistors (e.g., four 1.5mm gate width transistors instead of one 6mm transistor). This segmentation maintains the total gate periphery required for high power output while improving manufacturing yield, as smaller transistors have lower defect density and higher fabrication reliability.
2Power
If a large gate periphery GaN transistor is used to deliver high power, then the power output is improved, but unwanted oscillations are generated
Solution Approach 1:
By segmenting the large transistor into multiple smaller transistors, the patent reduces the gate periphery of each individual transistor, thereby minimizing the risk of unwanted oscillations that occur in large periphery devices while maintaining the required power output through parallel operation of the segmented transistors.
3Power
If dual power transistors are used in the peak path, then the gate periphery requirement is met, but push-pull type oscillations occur
Solution Approach 1:
The patent introduces asymmetric design elements to break the symmetry that causes push-pull oscillations. Specifically, the peak amplifiers are positioned at different distances from the hybrid coupler (one at 10mm, another at 20mm), and different impedance values are used in the output matching networks of the peak amplifiers. This asymmetric configuration disrupts the conditions for push-pull oscillations while maintaining the required power output.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The slot and transmission line configuration minimize oscillations, enhancing the stability and performance of the Doherty amplifier by reducing small-signal loop gain and suppressing sub-harmonic oscillations.
Implementation Method 1
The slot divides the peak output lead in a first part, a second part, and a common part. The first part is electrically connected to the first peak power transistor, and the second part is electrically connected to the second peak power transistor. The common part is arranged between the outer edge and the first and second parts and is integrally connected to the first and second parts. The slot ensures that the part of the peak RF signal amplified by the first peak power transistor combines with the part of the peak RF signal amplified by the second peak power transistor in the common part. The slot may have a length between 1/8 and 1/4 times a wavelength at or close to the operational frequency. The Applicant has found that by using the slot, the risk of push-pull type of oscillations can be minimized or at least lowered. This is at least in part due to the increased inductance associated with the paths from the outputs of the first and second peak power transistors to the common part of the peak output lead. The increased inductance causes the small-signal loop gain of the circuit including the first peak power transistor and second peak power transistor to be lowered, thereby improving the stability of the Doherty amplifier.
Data Source
AI summary
Example embodiments relate to Doherty amplifiers. One Doherty amplifier includes a packaged main amplifier that includes a main input lead for receiving a main RF signal, a main power transistor for amplifying the main RF signal, and a main output lead for outputting the main RF signal amplified by the main power transistor. The Doherty amplifier also includes a packaged peak amplifier that includes a peak input lead assembly for receiving a peak RF signal, a first peak power transistor configured for amplifying a part of the peak RF signal, a second peak power transistor configured for amplifying a remaining part of the peak RF signal, and a peak output lead for combining the part of the peak RF signal amplified by the first peak power transistor and the remaining part of the peak RF signal amplified by the second peak power transistor into an amplified peak RF signal.