Domain Controller Time Synchronization Across SoCs and MCUs
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Solution Overview
Problem
Current in-vehicle electronic architectures face challenges in achieving high precision time synchronization across multiple processors in domain controllers, particularly in autonomous driving systems, where scalability and diversity in time synchronization are limited by conventional methods like FlexRay buses, which are primarily designed for single electronic control units.
Innovation Solution
A time synchronization method and apparatus for domain controllers that utilize multiple interfaces such as UART/PPS, Ethernet, and FlexRay to receive and provide time services, allowing for flexible and scalable synchronization across multiple SoCs and MCUs, with a main SoC acting as a master clock and others as slave clocks within a precise clock synchronization protocol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional FlexRay bus is used for time synchronization, then single electronic control unit time synchronization can be achieved, but scalability and adaptability to multiple processors are poor
Solution Approach 1:
The domain controller is designed with multiple communication interfaces (Ethernet, FlexRay, CAN) that can each serve as time synchronization channels. This multi-functionality allows the system to adapt to different synchronization scenarios and external devices, resolving the contradiction between adaptability and complexity by making each interface versatile rather than dedicated to a single function
2Adaptability or versatility
If multiple interfaces (UART/PPS, Ethernet, FlexRay) are supported for time synchronization, then scalability and diversity improve, but device complexity increases
Solution Approach 1:
The main SoC acts as an intermediary or master clock that receives time services from external devices through multiple interfaces and distributes synchronized time to other SoCs and MCUs. This mediator approach manages the complexity of multiple interfaces by centralizing time synchronization coordination in the main SoC, allowing diverse interface support without proportionally increasing overall system complexity
3Power
If domain controller uses multiple processors (SoCs and MCUs) for high computing power, then autonomous driving capability improves, but time synchronization precision becomes more difficult to maintain
Solution Approach 1:
The domain controller is segmented into a main SoC that handles time synchronization as master clock and other SoCs/MCUs that act as slave clocks. This segmentation separates the time synchronization function from general computing functions, allowing multiple processors to maintain high computing power while the segmented time synchronization structure ensures precision through hierarchical clock distribution
Data Source
AI summary
A time synchronization method, apparatus, domain controller, and storage medium are disclosed. The domain controller is mounted in a vehicle and includes a number of SoCs and micro control units. The SoCs and micro control units are respectively, communicatively connected through the controller area network bus and respectively connected to the switch via Ethernet. The switch has external Ethernet interfaces. A main SoC in the number of SoCs has external UART/PPS interfaces and the micro control units have external FlexRay interfaces. The time synchronization method of the domain controller includes any one of the steps of receiving a time service from an external device through the UART/PPS interfaces, receiving a time service from the external device through the switch over the Ethernet interface, or receiving a time service from the external device through the FlexRay interface under a normal operation phase of the vehicle.