Domain Crossing Circuit With Two-Stage Latency Alignment
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Solution Overview
Problem
Conventional domain crossing circuits in semiconductor apparatuses face challenges in precisely aligning commands with clock signals, leading to degraded data output performance due to timing margins being reduced by excessive delay times, particularly when the variable delay time becomes small, causing the first pulse of the delay-locked loop clock signal to have a short or absent activation period.
Innovation Solution
A domain crossing circuit that includes a delay-locked loop block, a clock enable block, and a command pass block, which performs primary and secondary latency control using the delay-locked loop clock signal to align the read command signal with the clock signal, ensuring sufficient timing margins for stable and high-speed operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the variable delay time is reduced to achieve faster operation, then the operation speed is improved, but the timing margin is reduced causing the first pulse activation period to become short or absent
Solution Approach 1:
The latency control is divided into two independent stages: primary latency control using the internal clock signal ICLK, and secondary latency control using the delay-locked loop clock signal DLLCLK. This segmentation allows each stage to contribute to timing adjustment without compromising the other, enabling fast operation while preserving timing margins.
Solution Approach 2:
The delay-locked loop clock signal DLLCLK acts as an intermediary between the internal clock signal and the command signal. It provides an additional timing adjustment mechanism that compensates for the reduced timing margin caused by small variable delay times, ensuring reliable operation at high speeds.
2Device complexity
If conventional single-stage latency control is used, then the device complexity is reduced, but the command alignment precision with clock signal is insufficient
Solution Approach 1:
The latency control function is segmented into two distinct control blocks: a primary latency control block that processes commands using ICLK, and a secondary latency control block that refines timing using DLLCLK. This segmentation achieves precise command alignment while keeping each individual control block relatively simple.
Solution Approach 2:
The primary latency control performs preliminary timing adjustment on the command signal before it enters the secondary latency control stage. This preliminary action prepares the command signal for finer timing refinement, achieving high precision through a structured two-stage process.
Data Source
AI summary
A domain crossing circuit of a semiconductor apparatus includes a delay-locked loop block configured to generate a delay-locked loop clock signal in response to a clock signal and a clock enable signal; a clock enable block configured to generate the clock enable signal in response to the clock signal and a read command signal; and a command pass block configured to perform primary latency control according to the clock signal and secondary latency control according to the delay-locked loop clock signal, for the read command signal generated in response to a strobe signal, and generate a latency signal.