Domain-Splitting Interrupt Arbitration for Latency Reduction
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Solution Overview
Problem
Current computing systems experience increased latency and decreased bandwidth due to the need for programmable interrupt controllers (PICs) to examine all processors across the die, especially in multi-socket systems, leading to inefficiencies in interrupt distribution and cache line transfer.
Innovation Solution
The implementation of a domain-splitting approach where PICs are grouped into clusters within a common domain, leveraging a non-uniform memory access (NUMA) topology to allocate memory closer to CPUs, and using input/output NUMA (IONUMA) to optimize communication efficiency by processing low-priority interrupts within the same domain, reducing the need for global broadcasts and minimizing cache line transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PICs examine all processors across the die for interrupt arbitration, then interrupt distribution is comprehensive, but latency increases and bandwidth decreases
Solution Approach 1:
The patent divides the system into multiple domains, with each domain containing a subset of processors and associated PICs. Interrupt arbitration is performed locally within each domain rather than globally across all processors. This segmentation reduces the arbitration scope, thereby decreasing latency while maintaining reliable interrupt distribution through hierarchical domain management.
Solution Approach 2:
The patent introduces a hierarchical dimension to interrupt arbitration by organizing processors and PICs into multiple levels of domains. Low-priority interrupts are handled at the local domain level, while high-priority interrupts can escalate to higher levels. This dimensional organization reduces flat arbitration latency while preserving comprehensive interrupt distribution.
2Reliability
If global interrupt broadcasting is used across all processors, then interrupt coverage is complete, but communication efficiency decreases and cache line transfers increase
Solution Approach 1:
The patent segments the interrupt broadcasting mechanism into domain-specific broadcasts. Each domain's PICs broadcast interrupts only to processors within that domain, eliminating unnecessary global broadcasts. This segmentation maintains complete interrupt coverage for relevant processors while significantly improving communication efficiency by reducing redundant transmissions and cache line transfers.
3Reliability
If PICs are distributed across all processors, then interrupt handling is comprehensive, but device complexity increases
Solution Approach 1:
The patent segments the PIC distribution into domain-based clusters rather than universal distribution. Each domain contains PICs that manage interrupts for processors within that domain, reducing overall system complexity while maintaining comprehensive interrupt handling coverage through hierarchical domain management.
Data Source
AI summary
A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.