Dome-Shaped Metal Layer for Interconnect Resistivity Uniformity
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Solution Overview
Problem
Variations in trench width and depth during the formation of interconnect metal lines in semiconductor devices lead to undesirable variations in sheet resistivity, reducing manufacturing yield and device performance.
Innovation Solution
A method involving the formation of a metal layer with a dome-shaped profile over a semiconductor wafer using a plating process with virtual concentric electrodes, followed by a chemical mechanical polishing process to create interconnect lines with reduced thickness variations, resulting in increased sheet resistivity uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional CMP process is used to remove excess metal, then the planarization is achieved, but the temperature variation across the wafer causes more metal to be removed at the center than at the edges, resulting in thickness variation of interconnect lines
Solution Approach 1:
The patent applies preliminary action by forming a dome-shaped metal layer profile before the CMP process. The metal layer is intentionally deposited with greater thickness at the center and reduced thickness at the edges, so that when CMP removes material, the final interconnect lines achieve uniform thickness across the wafer despite temperature-induced variations in the polishing process.
Solution Approach 2:
The patent applies preliminary anti-action by pre-compensating for the harmful effect of temperature variation. Since higher temperature at the center causes excessive metal removal during CMP, the metal layer is initially formed with extra thickness at the center (dome shape) to counterbalance this effect, ensuring that after CMP, the interconnect lines have uniform thickness.
2Manufacturing precision
If the metal layer thickness is increased at the center to compensate for CMP over-removal, then the sheet resistivity uniformity is improved, but the metal layer requires a dome-shaped profile that increases process complexity
Solution Approach 1:
The patent applies local quality by creating a spatially non-uniform metal layer profile where the thickness varies across different regions of the wafer. The metal layer has greater thickness at the center region and reduced thickness at the edge regions, forming a dome-shaped profile. This localized variation in thickness is specifically designed to compensate for the non-uniform metal removal that occurs during CMP due to temperature gradients, thereby achieving uniform sheet resistivity across the entire wafer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves significant reduction in sheet resistivity variations across the wafer, enhancing manufacturing yield and device performance by ensuring uniform interconnect line thickness and resistivity.
Implementation Method 1
A plating process can then be used to deposit a metal, such as copper, in the trenches and over the dielectric layer
Implementation Method 2
A chemical mechanical polishing (CMP) process is typically used to remove excess metal over the trenches and form interconnect lines in the trenches
Data Source
AI summary
According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenches such that the metal layer has a dome-shaped profile over the wafer. The method further includes performing a planarizing process to form a number of interconnect lines, where each of the interconnect lines is situated in one of the trenches. The dome-shaped profile of the metal layer causes the interconnect lines to have a reduced thickness variation across the wafer after performing the planarizing process. The interconnect lines are situated in an interconnect metal layer, where the dome-shaped profile of the metal layer causes the interconnect metal layer to have increased sheet resistivity uniformity across the wafer after performing the planarizing process.


