Domino Logic Error Detection via Speculative Checker Nodes

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Solution Overview

Problem

Domino logic circuits face challenges in small process geometries due to noise, charge-sharing, leakage, and variability, leading to errors from late signals, incorrect keeper strength, and improper precharge settings, making them less suitable for modern integrated circuits.

Innovation Solution

An integrated circuit with built-in error detection circuitry that detects late discharge and partial discharge in domino logic, using speculative and checker nodes with precharge circuitry, logic circuitry, evaluation control circuitry, and error detection circuitry to provide robust operation and adjust parameters for reliable performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If domino logic is used in small process geometries, then high speed operation is achieved, but noise, charge-sharing, leakage and variability cause errors and reduce reliability

Engineering Contradiction:
Improveoperation speedVSAvoidcircuit reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by precharging the speculative node before the evaluation phase. The precharge circuitry prepares the node in advance with a known state, allowing the logic circuitry to evaluate input signals without being affected by previous states. This preliminary preparation ensures that even in small process geometries where leakage and noise are problematic, the node starts from a controlled state, improving reliability while maintaining high-speed operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary keeper circuit between the speculative node and the output. The keeper circuit acts as a mediator that maintains the node's state during the evaluation phase, isolating it from noise and leakage effects. This intermediary element buffers the node against harmful factors while allowing the logic evaluation to proceed, thus resolving the contradiction between speed and reliability in small process geometries.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If precharge voltage is increased to improve robustness, then error detection capability is enhanced, but power consumption increases

Engineering Contradiction:
Improveerror detection capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by using a dual-node approach where only the speculative node is fully precharged to detect errors, while the checker node uses a simpler detection mechanism. This partial application of high precharge voltage to only the necessary element (speculative node) provides error detection capability without proportionally increasing power consumption across the entire circuit. The checker node validates the result without requiring the same energy investment.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent creates a copy of the logic circuitry to evaluate the same inputs independently. The checker circuit replicates the evaluation function and compares its output with the speculative node's output. This copying approach allows error detection through comparison rather than through high-energy precharging of all nodes, reducing overall power consumption while maintaining robust error detection capability.

Inventive Principle:
Principle #26Copying

3Reliability

If speculative and checker nodes are added for error detection, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveerror detection reliabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the error detection function with the existing logic evaluation function by having the checker circuit perform the same logic evaluation as the main circuit. Instead of adding separate dedicated error detection circuits, the checker nodes are integrated into the logic flow, combining computational and validation functions in a single structure. This merging reduces the overall complexity compared to adding entirely separate error detection subsystems.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The checker nodes serve multiple functions: they evaluate the logic inputs like the speculative nodes, detect errors through comparison, and validate the output. This multi-functionality means that the additional hardware provides not just error detection but also redundant computation and output validation, justifying the increased complexity through enhanced reliability and versatility of the same circuit elements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8103922B2Error detection in precharged logic
Publication Date: 2012.01.24 ARM LTD
  • US8103922B2 patent drawing
  • US8103922B2 patent drawing
  • US8103922B2 patent drawing

AI summary

An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry have appropriate values. Error detection circuitry detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.