Domino Logic Block With Feedback Data Hold for Fast Evaluation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Domino logic circuits face challenges in maintaining data stability and operation speed due to delayed evaluation times and signal distortion caused by threshold voltages of NMOS transistors, especially when the operation voltage is low.
Innovation Solution
Incorporating a pre-charge circuit and an evaluation circuit with a feedback mechanism, including NAND gates, latches, and transistors, to pre-charge and discharge nodes based on clock and enable signals, allowing for selective propagation of input and feedback signals as output signals, thereby enhancing data hold functionality and reducing evaluation time delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If domino logic stages are serially connected to propagate signals without clocks assigned to each stage, then signal propagation speed is improved and multiple stages can be processed in one clock cycle, but data stability deteriorates due to delayed evaluation times and signal distortion from NMOS threshold voltages
Solution Approach 1:
The patent applies preliminary action by pre-charging nodes before the evaluation phase. The pre-charge circuit charges the internal nodes to a known state before the clock signal enables evaluation, ensuring that signal propagation starts from a stable condition. This pre-charging action compensates for the delayed evaluation caused by NMOS threshold voltage drops, maintaining both fast propagation and data stability across serially connected domino logic stages.
2Use of energy by moving object
If NMOS transistors are used in domino logic stages, then circuit size and power consumption are reduced, but signal distortion increases due to threshold voltage effects
Solution Approach 1:
The patent implements feedback by monitoring the voltage level at the internal node and using it to control the pre-charge transistor. When the node voltage drops due to NMOS threshold voltage effects, the feedback mechanism detects this and triggers a pre-charge action to restore the voltage level. This feedback loop compensates for signal distortion while maintaining the low power consumption benefits of NMOS transistors in the domino logic structure.
3Reliability
If evaluation time is extended to ensure accurate signal propagation through multiple stages, then data stability is improved, but operation speed deteriorates
Solution Approach 1:
The patent applies periodic action by using clocked pre-charge and evaluation phases. The pre-charge circuit operates periodically at the beginning of each clock cycle, quickly restoring node voltages before evaluation. This periodic pre-charging ensures that each domino logic stage has sufficient time for accurate evaluation while maintaining high operation speed across multiple serially connected stages, as the pre-charge action is concentrated in brief periodic intervals rather than continuously.
Data Source
AI summary
The domino logic of the general inventive concept receives a feedback signal and an input signal and outputs any one of the feedback signal and the input signal as an output signal in response to an enable signal and a clock signal. The feedback signal is an output signal of a previous cycle of a clock signal. When an enable signal is a first level, the domino logic maintains an output signal of a previous cycle instead of an input signal. According to the present general inventive concept, the domino logic having a data hold function can be embodied.