Pseudo-Static Domino Logic Clocking for Hold Timing Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Domino logic circuits face challenges with input pulse overlap and hold timing issues at clock cycle boundaries, leading to increased circuit complexity and power consumption, and conventional solutions result in signal processing delays and size problems.
Innovation Solution
A domino logic circuit design featuring a plurality of stages connected in series between a latch and a flip-flop, with a clock signal generator producing distinct duty cycles for the latch and flip-flop clock signals, allowing each stage to operate based on domino clock signals, and the flip-flop operates based on a separate flip-flop clock signal, facilitating pre-charging and evaluation phases to determine logic levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional domino logic circuits are used to achieve fast processing speed, then computational speed is improved, but input pulse overlap and hold timing issues occur at clock cycle boundaries
Solution Approach 1:
The clock signal is divided into multiple phases (first phase clock signal and second phase clock signal) with different duty cycles. The first domino logic circuit receives the first phase clock signal while the second domino logic circuit receives the second phase clock signal, segmenting the clock distribution to prevent pulse overlap and hold timing issues while maintaining fast processing speed.
2Reliability
If multiple phase overlapping clock signals are used to address timing problems, then timing accuracy is improved, but circuit complexity and size increase
Solution Approach 1:
The circuit employs dynamic clock signal phases where the first and second phase clock signals have different duty cycles that are dynamically optimized. This dynamic clocking approach achieves accurate timing control without requiring additional complex circuitry, as the timing precision is obtained through clock signal parameter optimization rather than increased circuit complexity.
3Reliability
If staticizing latches are used to convert domino pulses to static signals, then hold timing issues are avoided, but signal processing delays and power consumption increase
Solution Approach 1:
The circuit maintains the pulsed nature of domino logic by using periodically alternating clock phases instead of converting to static signals. The first and second phase clock signals alternately drive the respective domino logic circuits, providing hold timing stability through periodic clocking while avoiding the signal processing delays and power consumption penalties of staticizing latches.
Data Source
AI summary
A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal.