Domino Voltage Regulator Dual Loop Transient Response

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Solution Overview

Problem

Conventional low dropout (LDO) regulators are highly dependent on error amplifier offsets and voltage divider accuracy, leading to unstable output voltage and significant dropout voltage when switching between NMOS and PMOS transistors, especially under varying load conditions without external load capacitors.

Innovation Solution

Implementing two output voltage regulation loops, one using an NMOS transistor for small currents and another using a PMOS transistor for higher currents, with a current sense buffer to regulate the PMOS transistor's gate voltage when the NMOS transistor exceeds a specified threshold, allowing seamless transition and reduced dropout voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a single feedback loop with two error amplifiers is used to regulate output voltage, then the circuit can control both NMOS and PMOS pass devices, but the circuit becomes unstable due to offset between the two regulating loops

Engineering Contradiction:
Improveoutput voltage regulationVSAvoidcircuit stability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The single feedback loop is segmented into two independent regulation loops: a first loop using the error amplifier to regulate the NMOS pass device, and a second loop using a separate buffer amplifier to regulate the PMOS pass device. This segmentation eliminates the instability caused by offset between loops while maintaining independent control of each transistor.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit dynamically switches between NMOS and PMOS pass devices based on load conditions. The NMOS device is used for light load conditions, while the PMOS device is activated for heavy load conditions. This dynamic switching optimizes performance across different operating ranges without causing stability issues.

Inventive Principle:
Principle #15Dynamics

2Loss of energy

If the PMOS transistor is turned on to reduce dropout voltage under heavy load, then the output voltage can be maintained, but the circuit becomes dependent on error amplifier offset and voltage divider accuracy

Engineering Contradiction:
Improvedropout voltageVSAvoidoutput voltage accuracy
Core Design Contradiction:
Loss of energyVSMeasurement precision

Solution Approach 1:

A buffer amplifier is introduced as an intermediary between the feedback network and the PMOS pass device gate. This buffer amplifier provides accurate voltage control without being affected by the offset of the error amplifier or inaccuracies in the voltage divider, thereby maintaining output voltage precision while enabling low dropout voltage operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If external load capacitors are used to improve load transient regulation, then the output voltage stability improves, but the chip area increases

Engineering Contradiction:
Improveload transient regulationVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The regulator circuit uses its own internal components (the two pass devices and dual regulation loops) to provide load transient regulation without requiring external load capacitors. The fast response of the buffer amplifier and PMOS device combination provides inherent transient protection, eliminating the need for additional external components and reducing chip area.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8334681B2Domino voltage regulator (DVR)
Publication Date: 2012.12.18 DIALOG SEMICON GMBH
  • US8334681B2 patent drawing
  • US8334681B2 patent drawing
  • US8334681B2 patent drawing

AI summary

A low dropout voltage regulator comprising a first output voltage regulation loop with a NMOS transistor as a pass element and a second output voltage regulation loop with a PMOS transistor as a pass element. The NMOS transistor is used for small current loads up to 1 mA, the PMOS transistor is used for higher current loads from 1 mA and up. A current sense buffer senses the current through the NMOS transistor and controls the gate of the PMOS transistor accordingly. Good load transient operation is achieved without the need of an external load capacitor.