3D Integrated Circuit Fabrication via Donor Substrate Transfer
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Solution Overview
Problem
Conventional methods for fabricating three-dimensional integrated circuits are costly and inefficient, requiring significant materials and time, with increased resistance and signal delay due to chip stacking and thermal cycling, and excessive use of silicon wafers.
Innovation Solution
The method involves fabricating integrated circuits on an acceptor substrate without consuming it, using a donor substrate with implanted ions and plasma-activated bonding to form semiconductor foundation material, allowing for sequential layering and reduced thermal stress, and reusing the acceptor substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional chip stacking and bonding methods are used to improve chip density, then three-dimensional integrated circuits can be formed, but the fabrication cost increases significantly due to consumption of bulk substrates and excessive time expenditure
Solution Approach 1:
The patent applies the discarding and recovering principle by separating the circuit fabrication process from the bulk substrate consumption. Donor wafers are used to form circuit layers that are then transferred to acceptor substrates, allowing the expensive bulk substrates to be reused multiple times while the donor wafers are consumed. This resolves the contradiction by recovering and reusing the substrate material that would otherwise be discarded after single-use fabrication.
Solution Approach 2:
The invention segments the fabrication process into distinct stages: circuit formation on donor wafers, transfer to acceptor substrates, and substrate reuse. This segmentation allows the substrate to serve multiple purposes across different fabrication cycles, improving productivity while maintaining high chip density through the multi-level stacking approach.
2Quantity of substance
If conventional chip stacking is used to increase chip density, then multi-level circuits can be formed, but signal delay and resistance increase due to long signal paths
Solution Approach 1:
The patent transitions from planar two-dimensional circuit layouts to three-dimensional stacked architectures. By forming multiple circuit layers vertically stacked on acceptor substrates and using through-wafer vias for inter-layer connections, the invention reduces signal path length by allowing direct vertical connections between adjacent layers, thereby improving signal transmission quality while maintaining high chip density.
3Volume of moving object
If bottom-up approach with successive silicon layer growth is used to minimize design dimension, then multi-level circuits can be formed, but excessive fabrication time is required due to repeated thermal cycling and layer growth
Solution Approach 1:
The patent applies preliminary action by pre-forming complete circuit layers on donor wafers before transfer to acceptor substrates. This allows circuit fabrication to be completed in advance on optimized donor wafers, eliminating the need for repeated thermal cycling and slow silicon layer growth during the stacking process. The pre-formed layers are then transferred and stacked, significantly reducing overall fabrication time while achieving compact multi-level device dimensions.
4Manufacturing precision
If bulk silicon wafers are used for each circuit level fabrication, then complete circuit structures can be formed, but material consumption increases by twenty to thirty percent of total fabrication cost
Solution Approach 1:
The invention implements substrate recovery by using donor wafers for circuit formation and then transferring the completed circuit layers to acceptor substrates. The acceptor substrates can be reused multiple times for different circuit levels, while only the donor wafers are consumed. This dramatically reduces bulk substrate consumption and associated costs while maintaining complete and precise circuit structures through the transfer process.
Solution Approach 2:
The patent uses donor wafers as temporary copies or templates for circuit fabrication. The circuit patterns are formed on donor wafers, then transferred to the final acceptor substrates. This copying approach allows the expensive acceptor substrates to be reused without direct consumption, while the donor wafers serve as disposable templates that can be replaced for each circuit level.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces material consumption and fabrication time, minimizes signal delay, and enables efficient multi-level circuit formation with reduced dimensions and costs.
Implementation Method 1
a donor substrate with implanted ions
Implementation Method 2
plasma-activated bonding to form semiconductor foundation material
Data Source
AI summary
Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated. Integrated circuit devices formed by the methods are also disclosed.