Dopant Diffusion Blocking Superlattices for Semiconductor Contact Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face limitations in achieving enhanced charge carrier mobility and reduced contact resistance due to existing materials and processing techniques.
Innovation Solution
The use of dopant diffusion blocking superlattices with stacked groups of semiconductor and non-semiconductor monolayers to create a structure that reduces Schottky barrier height and contact resistance, incorporating materials like silicon and oxygen to enhance conductivity and mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor materials and processing techniques are used, then manufacturing simplicity is maintained, but charge carrier mobility and contact resistance performance are limited
Solution Approach 1:
The source and drain regions are segmented into multiple sub-regions with different doping concentrations by inserting dopant diffusion blocking superlattice layers at specific depths. This segmentation allows independent optimization of each region's electrical properties, achieving high charge carrier mobility through controlled dopant distribution while managing the complexity through systematic layering
Solution Approach 2:
Dopant diffusion blocking superlattice structures comprising alternating layers of different semiconductor materials (e.g., Si/SiGe) are employed to create composite regions within the source and drain. These composite materials provide both mechanical stability and tailored electrical characteristics, improving charge carrier mobility while maintaining structural integrity
2Reliability
If higher dopant concentration is used in source/drain regions, then conductivity is improved, but dopant diffusion into channel region increases causing performance degradation
Solution Approach 1:
Dopant diffusion blocking superlattice layers are inserted as intermediary structures between the heavily doped source/drain regions and the channel. These superlattice layers act as diffusion barriers that prevent dopant migration into the channel region, allowing high dopant concentrations in contact regions to be achieved without compromising dopant distribution control and channel performance
Solution Approach 2:
Different doping concentrations are applied to different regions within the source and drain by using dopant diffusion blocking superlattices at specific depths. The contact regions have high dopant concentration for low contact resistance, while the channel-adjacent regions have lower or blocked dopant concentration to maintain manufacturing precision and prevent performance degradation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved charge carrier mobility and reduced contact resistance, enabling higher performance in semiconductor devices with enhanced conductivity and mobility characteristics.
Implementation Method 1
dopant diffusion blocking superlattice
Implementation Method 2
The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices
Data Source
AI summary
A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.