Doped AlN-GaN Multilayer Substrate for Strain Management
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Solution Overview
Problem
Compound semiconductor transistors on Si or SiC substrates face lattice mismatching issues, leading to strain and unsatisfactory electric properties such as low switching speed and high-frequency performance due to differences in lattice constants and parasitic capacitance.
Innovation Solution
A multilayer substrate with alternating layers of doped carbon or transition element-modified compound semiconductors is used to buffer lattice mismatch, reducing parasitic capacitance and strain, comprising a base substrate, a multilayer with alternating AlN and GaN layers, and a device layer with a hetero junction structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Si or SiC substrates are used for compound semiconductor transistors, then cost and thermal conductivity are improved, but lattice mismatching causes strain and deteriorates electric properties
Solution Approach 1:
The substrate structure is segmented into multiple functional layers: base substrate (Si/SiC), buffer layer, AlN layers, GaN layers, and device layer. This segmentation allows each layer to address specific issues - the base substrate provides cost and thermal benefits, while the buffer and AlN/GaN layers progressively manage lattice mismatch and strain to protect electric properties.
Solution Approach 2:
Buffer layers and AlN layers serve as intermediary structures between the Si/SiC base substrate and the GaN device layer. These intermediaries gradually transition the lattice constant difference, reducing strain accumulation and protecting the electric properties of the transistor while enabling the use of cost-effective Si/SiC substrates.
2Reliability
If buffer structures are added to ease lattice mismatching, then strain is reduced, but parasitic capacitance increases and switching speed deteriorates
Solution Approach 1:
The thickness of AlN layers is precisely controlled within 1-10 nm range, and the number of AlN layers is optimized (1-10 layers). By changing these dimensional parameters, the patent achieves strain relief while minimizing parasitic capacitance. The thin AlN layers provide lattice mismatch management without creating excessive capacitive effects that would slow switching.
Solution Approach 2:
Different regions of the substrate structure have different qualities optimized for specific functions: the buffer layer region focuses on strain management, while the AlN/GaN multilayer region is optimized to minimize parasitic capacitance. This local optimization allows strain relief without sacrificing switching speed.
3Speed
If AlN layers are added to reduce parasitic capacitance, then switching speed is improved, but manufacturing complexity increases
Solution Approach 1:
The patent uses composite AlN/GaN multilayer structures where AlN provides low parasitic capacitance for high-speed performance, while GaN provides the semiconductor functionality. This composite approach achieves superior electric properties while the entire structure can be grown using standard epitaxial techniques, managing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances electric properties by relaxing strain, reducing parasitic capacitance, and improving switching speed and high-frequency performance while allowing the use of cost-effective silicon substrates with high breakdown voltage.
Implementation Method 1
Any compound semiconductors epitaxially grown on Si or SiC have lattice mismatching and therefore cause strain in the structure
Implementation Method 2
one selected from the group consisting of the first compound semiconductor and the second compound semiconductor being doped with one selected from the group consisting of carbon and transition elements
Implementation Method 3
A transistor having a hetero junction of compound semiconductors so as to generate two-dimensional electron gas is known as high-electron-mobility transistor
Implementation Method 4
As formation of the hetero junction in general requires epitaxy of good quality, single-crystalline GaN or sapphire is in general used as a substrate
Data Source
AI summary
A semiconductor device is formed on a semiconductor substrate, which is comprised of: a base substrate; and a multilayer being formed on the base substrate and having a surface serving for an interface with the semiconductor device, the multilayer including alternating layers of a first compound semiconductor and a second compound semiconductor materially distinguishable from the first compound semiconductor, one selected from the group consisting of the first compound semiconductor and the second compound semiconductor being doped with one selected from the group consisting of carbon and transition elements.