Impurity-Doped Amorphous Silicon Hard Mask for EUV Lithography
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Solution Overview
Problem
The challenge in semiconductor device fabrication is to reduce the thickness of the photoresist layer while maintaining high etching selectivity and productivity, especially with the introduction of extreme ultraviolet (EUV) lithography, where the existing techniques struggle to efficiently pattern fine widths and small pitches.
Innovation Solution
The method involves sequentially forming a first hard mask layer, a second hard mask layer, and a photoresist layer, where the second hard mask layer includes impurity-doped amorphous silicon, allowing for increased etching selectivity and reduced photoresist thickness, enabling efficient patterning and etching of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the thickness of the photoresist layer is reduced to improve productivity and enable finer pattern formation, then the etching selectivity and pattern formation capability improve, but the photoresist layer becomes too thin to maintain sufficient etching protection and pattern fidelity
Solution Approach 1:
The patent divides the hard mask structure into multiple layers (first hard mask layer, second hard mask layer, and third hard mask layer) with different materials and functions. The second hard mask layer made of impurity-doped amorphous silicon serves as an intermediate layer that enhances etching selectivity, allowing the photoresist layer to be thinner while maintaining sufficient etching protection through the segmented mask structure.
Solution Approach 2:
The patent employs a composite hard mask structure combining different materials: the first hard mask layer (e.g., silicon oxide or silicon nitride), the second hard mask layer (impurity-doped amorphous silicon), and the third hard mask layer (e.g., silicon oxide). This composite structure provides enhanced etching selectivity and mechanical support, enabling reduced photoresist thickness while maintaining pattern fidelity.
2Manufacturing precision
If impurity-doped amorphous silicon is used in the second hard mask layer to increase etching selectivity, then the etching rate and pattern definition improve, but the manufacturing process complexity increases
Solution Approach 1:
The patent changes the material parameters of the second hard mask layer by using impurity-doped amorphous silicon instead of undoped amorphous silicon or other materials. The doping introduces impurities that significantly enhance etching selectivity, allowing for better pattern definition and controlled etching rates, justifying the additional manufacturing steps.
Solution Approach 2:
The patent performs preliminary doping of the amorphous silicon layer with impurities before forming the complete hard mask structure. This preliminary action of doping the second hard mask layer in advance ensures that the material has the required etching properties before subsequent patterning and etching steps, simplifying the overall process control.
3Manufacturing precision
If a multi-layer hard mask structure is formed to enhance etching selectivity, then the pattern formation quality improves, but the fabrication time and production costs increase
Solution Approach 1:
The patent merges the formation of the second hard mask layer (impurity-doped amorphous silicon) with the existing hard mask layer sequence, integrating it between the first and third hard mask layers. This merging approach allows the enhanced etching selectivity to be achieved without completely redesigning the fabrication process, thereby reducing the additional time required compared to implementing a separate complex masking system.
Data Source
AI summary
Methods for fabricating a semiconductor device are provided including sequentially forming a first hard mask layer, a second hard mask layer and a photoresist layer on a target layer, patterning the photoresist layer to form a photoresist pattern, sequentially patterning the second hard mask layer and the first hard mask layer using the photoresist pattern as an etching mask to form a first hard mask pattern and a second hard mask pattern on the first hard mask pattern, and etching the target layer using the first hard mask pattern and the second hard mask pattern as an etching mask, wherein the second hard mask layer includes impurity-doped amorphous silicon.