Doped CESL Contact Openings for Precise Dielectric Etching

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor devices continue to integrate more components into a given area with reduced minimum feature sizes, challenges arise in efficiently etching through dielectric layers and etch stop layers without damaging underlying structures.

Innovation Solution

A method involving a breakthrough implant process using dopants like argon or fluorine to disrupt the crystalline structure of etch stop layers, followed by a selective wet etch process with recess chemicals, enhances the etching process by increasing selectivity and reducing lateral etching, allowing precise formation of openings for interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etching processes are used to etch through dielectric layers and etch stop layers, then the etching can proceed through the layers, but lateral etching occurs and structural integrity is compromised

Engineering Contradiction:
Improveetching precisionVSAvoidlateral etching damage
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

A dopant implantation step is performed before the etching process to modify the etch stop layer. This preliminary action creates a doped region with different etch selectivity, allowing the etch to proceed vertically through the dielectric layer while stopping at the doped region, thereby preventing lateral etching and maintaining structural integrity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etch stop layer is locally modified by dopant implantation only in the region where precise etching is needed. This creates a localized change in material properties (etch selectivity) without affecting the entire layer, enabling precise control over where and how the etching proceeds while protecting surrounding structures

Inventive Principle:
Principle #3Local quality

2Productivity

If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but etching through dielectric layers becomes more difficult and selective

Engineering Contradiction:
Improveintegration densityVSAvoidetching selectivity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The etch selectivity is enhanced by changing the material parameters of the etch stop layer through dopant implantation. By introducing dopants that alter the chemical composition and structure of the etch stop layer, the etch process achieves higher selectivity between the dielectric layer and the stop layer, enabling precise etching at reduced feature sizes with better control over etch depth and profile

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the precision and efficiency of etching through dielectric layers, maintaining structural integrity and reducing RC delay, thereby enhancing the performance and reliability of semiconductor devices.

Implementation Method 1

performing a dopant implantation in the target region

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

performing an etch to remove a portion of the etch stop layer materials in the target region

Methodology Applied
Scientific EffectChemical etching:

Data Source

PatentUS20250336719A1Semiconductor device with doped region dielectric layer
Publication Date: 2025.10.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250336719A1 patent drawing
  • US20250336719A1 patent drawing
  • US20250336719A1 patent drawing

AI summary

Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.