Doped Conductive Interconnects for Microelectronic Packaging
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Solution Overview
Problem
Microelectronic packaging technologies face challenges in achieving reliable adhesion and preventing stress-related defects, such as trace lifting, during substrate plating processes, especially as device features are scaled down.
Innovation Solution
Incorporating dopants like magnesium, zirconium, and zinc in the plating process for conductive interconnect structures, which enhances their superplasticity and ductility, reducing the likelihood of stress-induced defects by allowing grain growth and rotation, thereby improving adhesion and mechanical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional plating processes are used for conductive interconnect structures, then manufacturing simplicity is maintained, but adhesion reliability deteriorates due to trace lifting and stress-related defects
Solution Approach 1:
The patent applies parameter changes by modifying the chemical composition of the plating bath through the addition of specific dopants (magnesium, zirconium, or zinc) at controlled concentrations (0.05-10% weight). This changes the physical and mechanical properties of the deposited conductive interconnect structure, enhancing its superplasticity and ductility while maintaining adhesion reliability and preventing trace lifting defects
Solution Approach 2:
The patent creates a composite material system by incorporating dopant elements (magnesium, zirconium, or zinc) into the conductive interconnect structure during the plating process. This results in a composite conductive layer with improved mechanical properties, including enhanced elongation to failure and stress resistance, while maintaining electrical conductivity and adhesion to the substrate
2Productivity
If device features are scaled down for higher processor performance, then processing capability is improved, but stress-related defects increase
Solution Approach 1:
The patent modifies the microstructural parameters of the conductive interconnect structure by controlling grain size through dopant addition. The dopants refine the grain structure and enhance superplasticity, allowing the scaled-down features to better withstand stress without failure, thereby maintaining reliability as device dimensions are reduced
Solution Approach 2:
The patent creates a composite conductive material with enhanced mechanical properties through dopant incorporation. This composite structure provides improved stress resistance and ductility in scaled-down interconnect features, enabling higher processor performance while maintaining reliability against stress-related defects
3Reliability
If dopants are added to enhance superplasticity and ductility, then adhesion and stress resistance are improved, but manufacturing complexity increases
Solution Approach 1:
The patent modifies the plating bath composition by adding dopants at relatively high concentrations (0.05-10% weight), which significantly enhances the superplasticity and ductility of the deposited conductive interconnect structure. This parameter change improves mechanical reliability and adhesion while the broad concentration range allows for flexible process optimization
Solution Approach 2:
The patent creates a composite conductive material system with enhanced mechanical reliability through dopant incorporation. The composite structure provides improved adhesion and stress resistance, and the process integrates seamlessly into conventional plating operations, requiring only modification of the bath composition rather than fundamental process changes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The addition of these dopants significantly increases the elongation to failure of conductive interconnect structures, reduces grain size, and enhances their ability to withstand stress, minimizing trace lifting and other defects, thus improving the reliability and yield of microelectronic devices.
Implementation Method 1
The conductive structures of the various embodiments disclosed herein enable superplasticity of the conductive interconnect structures
Data Source
AI summary
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming an opening in a dielectric material of a package substrate, and then plating a conductive interconnect structure in the opening utilizing a plating process. The plating process may comprises a conductive metal and a dopant comprising between about 0.05 and 10 percent weight, wherein the dopant comprises at least one of magnesium, zirconium and zinc.