Doped Dielectric Memory Cell Structure for Uniform 3D Channel Doping
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Solution Overview
Problem
Three-dimensional (3D) memory devices face challenges in achieving uniformity and consistent electrical properties due to non-uniform semiconductor material doping, particularly with shrinking volumes and multiple layers, leading to inconsistent performance.
Innovation Solution
The use of doped dielectric materials for electrostatic doping in 3D memory devices, combined with epitaxial growth of single crystal silicon layers on silicon germanium substrates, creates a uniform cell structure with reduced leakage and improved electrostatic control, resulting in better I-on, I-off performance and lower off-current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional semiconductor material doping methods are used in 3D memory devices, then manufacturing process is simpler, but doping uniformity deteriorates due to shrinking volumes and multiple layers
Solution Approach 1:
The patent changes the doping method from traditional ion implantation or diffusion to electrostatic doping using doped dielectric materials. This parameter change enables uniform doping in shrinking 3D structures by using electric fields to control carrier distribution, achieving consistent doping profiles across multiple layers without the limitations of traditional thermal or implantation-based methods
Solution Approach 2:
The patent introduces doped dielectric materials as intermediary elements between gate electrodes and channel regions. These doped dielectric layers act as mediators to provide electrostatic doping to the semiconductor channels, enabling precise control of carrier concentration and improving doping uniformity in complex 3D structures
2Reliability
If doped dielectric materials are used for electrostatic doping, then doping uniformity and electrostatic control are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the device structure into distinct functional layers including doped dielectric layers, undoped dielectric layers, gate electrodes, and channel regions. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall manufacturing feasibility through standardized fabrication processes
Solution Approach 2:
The patent employs composite material structures combining doped dielectric materials with undoped dielectric materials and semiconductor layers. This composite approach enables simultaneous achievement of electrostatic doping control, electrical isolation, and mechanical stability, improving reliability while managing fabrication complexity through material property complementarity
3Object-generated harmful factors
If uniform cell structure is achieved through epitaxial growth, then leakage current is reduced, but manufacturing time and cost increase
Solution Approach 1:
The patent performs preliminary epitaxial growth of single crystal silicon layers on silicon germanium substrates before subsequent device fabrication steps. This preliminary action creates a uniform crystal structure that minimizes defects and leakage pathways from the outset, reducing the need for corrective processing and ultimately decreasing total fabrication time
Solution Approach 2:
The patent applies local quality enhancement by using epitaxial growth specifically in regions where uniformity is critical for reducing leakage, while other regions may use different fabrication approaches. This targeted application of epitaxial growth optimizes the balance between leakage reduction and manufacturing efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved drivability, reduced leakage current, and enhanced subthreshold slope, providing more cost-effective and reliable 3D memory devices with consistent electrical properties.
Implementation Method 1
The use of doped dielectric materials for electrostatic doping in 3D memory devices
Implementation Method 2
epitaxial growth of single crystal silicon layers on silicon germanium substrates
Data Source
AI summary
Systems, methods and apparatus are provided for three-dimensional memory devices, including an array of vertically stacked memory cells having: access devices each respectively including: a semiconductor material comprising a first source/drain region and a second source/drain region separated by a respective channel region, and a respective gate opposing the respective channel region and separated therefrom by a respective gate dielectric; a respective first doped dielectric material adjacent to the respective gate and the respective semiconductor material; and a respective second doped dielectric material adjacent to the respective gate and the respective semiconductor material, wherein the respective second doped dielectric material is opposite to the respective first doped dielectric material relative to the respective gate; storage nodes electrically coupled to the respective second source/drain regions of the access devices.