Impurity-Doped DRAM Isolation Structure for HEIP Suppression

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Solution Overview

Problem

Dynamic random access memory (DRAM) devices face challenges in shrinking memory cell area due to charge trapping in isolation structures, leading to leakage current and hot-electron-induced punchthrough (HEIP) effects, which existing solutions either increase device size or complicate integration processes.

Innovation Solution

Incorporating a charge trapping layer doped with impurities in the isolation structure, specifically silicon nitride, to terminate dangling bonds and reduce HEIP effects, while maintaining a compact device size by applying impurities selectively to the dielectric layers within the trench structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a charge trapping layer is used in the isolation structure, then the isolation effect is improved, but charge trapping occurs leading to leakage current and HEIP effect

Engineering Contradiction:

Improveisolation effectVSAvoidcharge trapping and leakage current

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent converts the harmful charge trapping effect into a beneficial one by intentionally doping the charge trapping layer with impurities. The dopants fill the trap states that would otherwise capture charges and cause leakage, transforming the layer from a harmful charge trap into a controlled impurity region that prevents unwanted charge accumulation while maintaining isolation functionality.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent changes the electrical parameters of the charge trapping layer by introducing impurity doping. This modifies the layer's electrical characteristics, specifically filling the trap states and altering the charge distribution, thereby eliminating the HEIP effect and leakage current while preserving the isolation structure's fundamental properties.

Inventive Principle:

Principle #35Parameter changes

2Area of moving object

If the memory cell area is shrunk, then the device size is reduced, but charge trapping in isolation structures increases leading to leakage current

Engineering Contradiction:

Improvememory cell areaVSAvoidcharge trapping and leakage current

Core Design Contradiction:

Area of moving objectVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by selectively doping only the charge trapping layer within the isolation structure, while leaving other regions unchanged. This localized impurity introduction targets specifically the area where charge trapping occurs, allowing memory cell shrinkage without compromising isolation performance in other parts of the device.

Inventive Principle:

Principle #3Local quality

3Object-generated harmful factors

If existing solutions are applied to reduce HEIP effect, then leakage current is reduced, but device size increases or integration process becomes complicated

Engineering Contradiction:

ImproveHEIP effect and leakage currentVSAvoiddevice size and integration process

Core Design Contradiction:

Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent merges the charge trapping layer formation with the isolation structure fabrication process. By doping the charge trapping layer during the isolation structure creation, the method eliminates the need for separate HEIP mitigation steps, thereby reducing device complexity and simplifying the integration process between cell and peripheral regions while effectively reducing leakage current.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The doping of impurities in the charge trapping layer effectively reduces HEIP effects, improving device performance without increasing the size of the semiconductor device and simplifying the integration process between cell and peripheral regions.

Implementation Method 1

The charge trapping layer is doped with an impurity

Methodology Applied

Scientific EffectDoping: Dopants

Implementation Method 2

The lone pair of electrons of silicon in silicon nitride may form a dangling bond, trapping charges (e.g., charges) and thus inducing hot-electron-induced punchthrough (HEIP) effect

Methodology Applied

Scientific EffectHot-electron-induced punchthrough effect:

Data Source

PatentUS20240347374A1Semiconductor device including isolation structure with impurity and method for manufacturing the same

Publication Date: 2024.10.17 NAN YA TECH

AI summary

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate and a first isolation structure. The substrate has a cell region and a peripheral region. The first isolation structure is disposed in the cell region of the substrate. The first isolation structure includes a first dielectric layer and a second dielectric layer. The second dielectric layer is spaced apart from the substrate by the first dielectric layer. The second dielectric layer is doped with an impurity.