Doped Epitaxial Source/Drain Tips for MOSFET Parasitic Resistance

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Solution Overview

Problem

Existing semiconductor technologies face challenges in controlling dopant concentration and location, particularly in the source/drain extension regions of MOSFETs, which limits the improvement of electron mobility and increases parasitic resistance.

Innovation Solution

The implementation of a Self-aligned Epi Tip (SET) architecture using in-situ carbon and phosphorus doped silicon epitaxial regions, deposited via a cyclical deposition-etch process, to form source and drain epi-tip regions in close proximity to the channel region, enhancing electron mobility and reducing parasitic resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If dopant implantation and diffusion method is used to dope source/drain extension regions, then dopant can be introduced into the regions, but the dopant concentration and location cannot be precisely controlled

Engineering Contradiction:
Improvedopant concentration and location controlVSAvoiddoping process complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent forms epitaxial regions with predetermined dopant concentration and location before forming the source and drain regions. This preliminary doping action during the epitaxial growth process allows precise control of dopant distribution in the source/drain extension regions, eliminating the need for subsequent implantation and diffusion steps while achieving better manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the doping function from the traditional implantation and diffusion process and integrates it into the epitaxial growth process. By taking out the doping step from the conventional sequence and performing it concurrently with epitaxial region formation, the method achieves precise dopant control while simplifying the overall manufacturing process.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If dopant implantation is used to reduce parasitic resistance, then resistance can be reduced, but lateral undercut and parasitic resistance at tip regions remain unaddressed

Engineering Contradiction:
Improveparasitic resistance reductionVSAvoidlateral undercut and tip region parasitic resistance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent forms epitaxial regions with different dopant concentrations at different locations within the source and drain structures. The method creates locally optimized doping profiles where high-doped epitaxial regions are positioned precisely at the tip regions and source/drain extension areas, providing local quality enhancement that reduces parasitic resistance and addresses lateral undercut issues specific to those critical regions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the dopant concentration parameter during the epitaxial growth process by introducing dopants at specific stages. This parameter change allows the formation of regions with varying dopant concentrations - lightly doped bulk regions and heavily doped tip regions - thereby reducing parasitic resistance where it matters most while maintaining proper junction characteristics.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly enhances transistor performance by increasing electron mobility, reducing short channel effects, and lowering parasitic resistance, thereby improving drive current.

Implementation Method 1

an epitaxial region is deposited over each of the recessed source and drain interfaces by alternatingly exposing the substrate to a first precursor and a second precursor

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

the first precursor and the second precursor are alternated for a plurality of cycles to form the epitaxial region and to remove amorphous material deposited on the spacers

Methodology Applied
Scientific EffectCyclical deposition-etch:

Data Source

PatentUS12294027B2Semiconductor device having doped epitaxial region and its methods of fabrication
Publication Date: 2025.05.06 INTEL CORP
  • US12294027B2 patent drawing
  • US12294027B2 patent drawing
  • US12294027B2 patent drawing

AI summary

Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.