Doped Ferroelectric Capacitor Stack for Low-Voltage Nonvolatile Memory
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Solution Overview
Problem
Conventional semiconductor memory technologies face challenges in achieving high remnant polarization and low coercive voltage for ultra-low voltage operation, particularly in advanced technology nodes, where maintaining nonvolatility and high cycling endurance is crucial.
Innovation Solution
A semiconductor device with a capacitor comprising a polar layer doped with a metal element that differs from the base polar material, featuring crystalline conductive oxide electrodes and barrier metal layers, engineered to achieve a ferroelectric switching voltage and remnant polarization suitable for nonvolatile memory applications, with a ferroelectric oxide layer having a lattice constant matched to the electrodes and a thickness optimized for low voltage switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric materials are used in DRAM capacitors, then the device can operate with simple structure, but the leakage current is high and data is lost when powered off
Solution Approach 1:
The patent changes the fundamental parameter of the dielectric material from conventional materials to ferroelectric material, which exhibits spontaneous polarization and hysteresis loop characteristics. This parameter change enables the capacitor to retain data without power while reducing leakage current, as the ferroelectric material maintains its polarization state due to its inherent material properties rather than relying on continuous power supply.
Solution Approach 2:
The patent employs composite material structures including ferroelectric material combined with conductive oxide electrodes and barrier metal layers. This composite approach optimizes both the ferroelectric properties for data retention and the electrical properties for low leakage, achieving high reliability while minimizing energy loss through the synergistic combination of different materials.
2Reliability
If ferroelectric material is used to achieve nonvolatile memory, then data retention is improved, but the coercive voltage is high which slows down switching speed
Solution Approach 1:
The patent applies local quality by using conductive oxide electrodes with high conductivity specifically at the electrode interfaces with the ferroelectric material. This localized improvement in electrical conductivity at critical interfaces reduces the overall coercive voltage required for switching, thereby increasing switching speed while maintaining the bulk ferroelectric material's data retention properties.
Solution Approach 2:
The patent modifies the electrical parameters of the capacitor by introducing barrier metal layers and conductive oxide electrodes that change the electric field distribution and reduce interfacial resistance. These parameter changes lower the coercive voltage of the ferroelectric capacitor, enabling faster switching speeds while preserving nonvolatile data retention capabilities.
3Area of stationary object
If device footprint is scaled down to reduce size, then integration density is improved, but leakage current increases and remnant polarization decreases
Solution Approach 1:
The patent uses composite material structures with conductive oxide electrodes and barrier metal layers that maintain low leakage current even in scaled-down devices. The conductive oxide provides high conductivity to compensate for reduced dimensions, while the barrier metal layers prevent leakage paths, enabling miniaturization without proportionally increasing leakage current.
Solution Approach 2:
The patent changes the material parameters of the electrodes and interfaces to maintain optimal electrical properties in scaled devices. By using conductive oxide with tunable conductivity and barrier metals with appropriate work functions, the patent compensates for the reduced device dimensions, maintaining low leakage current and high remnant polarization despite smaller footprint.
4Area of stationary object
If device footprint is scaled down to reduce size, then integration density is improved, but remnant polarization decreases affecting memory reliability
Solution Approach 1:
The patent applies local quality by optimizing the interface properties between the ferroelectric material and electrodes through conductive oxide layers. This localized optimization at the critical interfaces maintains high remnant polarization even when the overall device size is reduced, as the improved interfacial quality compensates for the reduced volume of the ferroelectric material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables fast, low-voltage switching with high remnant polarization, enhancing the nonvolatility and cycling endurance of semiconductor memory devices, addressing the limitations of conventional technologies in advanced technology nodes.
Implementation Method 1
a polar layer comprising a base polar material doped with a dopant
Implementation Method 2
ferroelectric materials and semiconductor devices incorporating the same
Data Source
AI summary
The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.