Selective Growth of Doped Group IV-Sn Layers

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Solution Overview

Problem

Existing methods for doping Group IV-Sn semiconductor materials, such as GeSn, face challenges in achieving shallow junctions and limited thermal budgets, particularly with Boron implantation in GeSn, where the activation of dopants is hindered by the need for low-temperature annealing to prevent Sn precipitation.

Innovation Solution

The method involves selective deposition of highly doped Group IV-Sn semiconductor materials using a precursor like SnCl4 as both a Sn source and a selective growth regulator, combined with a dopant precursor like B2H6, in a cyclic deposition-etch process, allowing for the growth of monocrystalline material on semiconductor regions while removing polycrystalline material from insulator regions, all at low processing temperatures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Boron implantation is used to dope GeSn, then dopant activation can be achieved, but Sn precipitation occurs due to the high temperature annealing required

Engineering Contradiction:
Improvedopant activationVSAvoidSn precipitation
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent replaces the thermal field (annealing) with a chemical field (in-situ CVD deposition). Instead of using high-temperature annealing to activate dopants, the method incorporates dopants directly during the chemical vapor deposition process, eliminating the need for thermal activation and thus preventing Sn precipitation while achieving dopant activation simultaneously.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent performs dopant incorporation during the deposition process itself, before any annealing step would be required. By pre-incorporating the dopants (such as Boron) into the GeSn lattice during CVD growth, the material achieves the desired doping without subsequent high-temperature processing that would cause Sn precipitation.

Inventive Principle:
Principle #10Preliminary action

2Object-affected harmful factors

If low temperature annealing is used to prevent Sn precipitation, then Sn precipitation is avoided, but dopant activation is limited

Engineering Contradiction:
ImproveSn precipitationVSAvoiddopant activation
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent replaces the thermal activation mechanism with a chemical incorporation mechanism. During CVD deposition, dopant precursors are introduced into the reaction chamber where they are chemically incorporated into the growing GeSn crystal lattice at low temperatures (below 600°C). This chemical field approach substitutes for the thermal field approach, enabling dopant activation without high-temperature annealing.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental parameter of how dopants are activated - from thermal activation (temperature-dependent) to chemical activation (concentration-dependent). By controlling the partial pressure and flow rate of dopant precursors during CVD, the dopant concentration in the final material is directly controlled, achieving high dopant activation at low temperatures where Sn precipitation is avoided.

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If implantation method is used for doping, then dopant can be introduced, but shallow junctions are difficult to achieve

Engineering Contradiction:
Improvedopant introductionVSAvoidshallow junction depth
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent replaces the mechanical implantation process (physical bombardment of dopant ions) with a chemical deposition process. In the CVD method, dopant-containing vapor species are transported to the substrate surface and incorporated into the growing film. This chemical transport and incorporation mechanism provides superior depth control and enables shallow junction formation, as the dopants are incorporated throughout the film thickness during growth rather than being implanted to a fixed depth by ion range.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the selective deposition of doped Group IV-Sn layers with high dopant concentrations at temperatures below 650°C, facilitating the growth of monocrystalline doped GeSn with enhanced selectivity and dopant incorporation, overcoming the limitations of traditional implantation methods.

Implementation Method 1

providing a precursor of the group IV semiconductor material, SnCl4 acting at the same time as a Sn precursor and a selective growth regulator

Methodology Applied
Scientific EffectSelective growth regulation: Chemical Vapour Deposition

Implementation Method 2

etching back the deposited doped group IV-Sn layer using an etch gas until the layer is substantially completely removed from the second region

Methodology Applied
Scientific EffectChemical etching: Chemical Vapour Deposition

Implementation Method 3

During deposition, monocrystalline doped group IV-Sn material may be grown on the first region and polycrystalline doped group IV-Sn material may be grown on the second region

Methodology Applied
Scientific EffectMonocrystalline growth: Epitaxy

Data Source

PatentUS9263263B2Method for selective growth of highly doped group IV—Sn semiconductor materials
Publication Date: 2016.02.16 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
  • US9263263B2 patent drawing
  • US9263263B2 patent drawing

AI summary

Disclosed are methods for selective deposition of doped Group IV-Sn materials. In some embodiments, the method includes providing a patterned substrate comprising at least a first region and a second region, where the first region includes an exposed first semiconductor material and the second region includes an exposed insulator material, and performing at least two cycles of a grow-etch cyclic process. Each cycle includes depositing a doped Group IV-Tin (Sn) layer, where depositing the doped Group IV-Sn layer includes providing a Group IV precursor, a Sn precursor, and a dopant precursor, and using an etch gas to etch back the deposited doped Group IV-Sn layer.