Doped High-K Gate Structures for Multi-Threshold Scaled FETs
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to efficiently produce field effect transistors (FETs) with low and ultra-low threshold voltages while maintaining cost-effectiveness and scalability, as the constraints on work function metal layer thicknesses and deposition become increasingly difficult with continuous scaling down of FETs.
Innovation Solution
The method involves forming NFETs and PFETs with similar work function metal layer thicknesses but different threshold voltages on the same substrate by controlling the types and concentrations of metal dopants in high-K gate dielectric layers, which induce dipoles of varying polarities and concentrations at the interfaces, thereby adjusting the effective work function values and threshold voltages without altering the work function metal layer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If FET dimensions are continuously scaled down to achieve higher storage capacity and faster processing, then device performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent changes the chemical composition parameters of the gate dielectric layer by incorporating metal dopants (such as Al, Ga, In, La, Y) to modify the effective work function. This allows adjustment of threshold voltage without changing the physical dimensions of the FET, thereby maintaining high performance while avoiding the complexity of continuous scaling
Solution Approach 2:
The patent uses composite gate dielectric structures combining high-K dielectric materials with metal dopants. This composite approach enables multiple threshold voltages to be achieved within a single material system, simplifying the manufacturing process compared to separate processing steps for different FET types
2Length of moving object
If work function metal layer thickness is reduced to maintain scaling, then device dimensions are reduced, but deposition constraints and manufacturing difficulty increase
Solution Approach 1:
The patent changes the material composition of the gate dielectric layer by adding metal dopants, which modifies the effective work function value. This allows the threshold voltage to be adjusted without changing the thickness of the work function metal layer, thereby maintaining ease of deposition while achieving different threshold voltages
Solution Approach 2:
The patent extracts the work function adjustment function from the work function metal layer thickness and transfers it to the gate dielectric layer composition. By incorporating dopants directly into the gate dielectric, the need to precisely control thin metal layer thickness is eliminated, simplifying manufacturing
3Adaptability or versatility
If different threshold voltages are produced using traditional methods, then device functionality is achieved, but manufacturing cost and time increase
Solution Approach 1:
The patent creates a universal gate dielectric layer formulation that can produce multiple different threshold voltages by simply changing the metal dopant composition. A single deposition process can yield different threshold voltages (e.g., 0.8V, 1.0V, 1.2V) by adjusting dopant types and concentrations, eliminating the need for separate processing lines for different FET types
Solution Approach 2:
The patent uses compositional parameters of the gate dielectric layer (metal dopant type and concentration) to control threshold voltage. This allows a single manufacturing process to produce multiple threshold voltage levels by adjusting material composition rather than repeating physical deposition steps, significantly reducing manufacturing cost and time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the cost-effective and time-efficient production of FETs with different threshold voltages, reducing manufacturing costs by 20-30% and time by 15-20%, while achieving much smaller dimensions and reliable gate structures.
Implementation Method 1
controlling the types and concentrations of metal dopants in high-K gate dielectric layers, which induce dipoles of varying polarities and concentrations at the interfaces, thereby adjusting the effective work function values and threshold voltages
Data Source
AI summary
A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The semiconductor device includes a first gate structure and a second gate structure. The first gate structure includes a first interfacial oxide (IO) layer, a first high-K (HK) dielectric layer disposed on the first interfacial oxide layer, and a first dipole layer disposed at an interface between the first IL layer and the first HK dielectric layer. The HK dielectric layer includes a rare-earth metal dopant or an alkali metal dopant. The second gate structure includes a second IL layer, a second HK dielectric layer disposed on the second IL layer, and a second dipole layer disposed at an interface between the second IL layer and the second HK dielectric layer. The second HK dielectric layer includes a transition metal dopant and the rare-earth metal dopant or the alkali metal dopant.