Doped Interlayer Insulating Layers for Uniform Contact Plug Etching
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Solution Overview
Problem
Current semiconductor devices with interlayer insulating layers face challenges in achieving uniform contact plug widths due to varying doping concentrations, leading to non-uniform etching rates and potential exposure issues of gate electrodes during manufacturing.
Innovation Solution
The semiconductor device incorporates doped interlayer insulating layers with gradually increasing doping concentrations towards the staircase structures, allowing for controlled etching rates and uniform contact plug widths by forming multiple doping regions within the interlayer insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a uniform doping concentration is used in the interlayer insulating layer, then the manufacturing process is simple, but the etching rate is non-uniform leading to non-uniform contact plug widths
Solution Approach 1:
The interlayer insulating layer is designed with non-uniform doping concentration, where the doping concentration varies at different locations (higher near the gate electrode, lower at the top surface). This local quality variation ensures uniform etching rate throughout the contact hole formation process, resulting in uniform contact plug widths despite the increased structural complexity.
Solution Approach 2:
The doping concentration parameter is changed across different regions of the interlayer insulating layer. By controlling the doping concentration to be higher near the gate electrode and lower at the top surface, the etching rate is compensated for the varying depths, achieving uniform contact plug widths through parameter optimization rather than uniform doping.
2Reliability
If the interlayer insulating layer is etched to expose gate electrodes, then electrical contact is enabled, but non-uniform etching rates may cause exposure issues and manufacturing defects
Solution Approach 1:
The interlayer insulating layer is designed with non-uniform doping concentration, where the doping concentration varies at different locations (higher near the gate electrode, lower at the top surface). This local quality variation ensures uniform etching rate throughout the contact hole formation process, resulting in uniform contact plug widths despite the increased structural complexity.
Solution Approach 2:
The doping concentration parameter is changed across different regions of the interlayer insulating layer. By controlling the doping concentration to be higher near the gate electrode and lower at the top surface, the etching rate is compensated for the varying depths, achieving uniform contact plug widths through parameter optimization rather than uniform doping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of the semiconductor device by ensuring consistent contact plug widths and improved exposure of gate electrodes, thereby reducing manufacturing complexities and increasing device reliability.
Implementation Method 1
a lower interlayer insulating layer doped with an impurity and covering the lower staircase structure, the lower interlayer insulating layer having a doping concentration gradually increasing toward the lower staircase structure
Data Source
AI summary
A semiconductor device includes a lower memory stack disposed on a substrate and including lower gate electrodes and a lower staircase structure, an upper memory stack including upper gate electrodes and an upper staircase structure, a lower interlayer insulating layer doped with an impurity and covering the lower staircase structure, the lower interlayer insulating layer having a doping concentration gradually increasing toward the lower staircase structure, an upper interlayer insulating layer doped with an impurity and covering the upper staircase structure and the lower interlayer insulating layer, the upper interlayer insulating layer having a doping concentration gradually increasing toward the upper staircase structure and the lower interlayer insulating layer, lower contact plugs and upper contact plugs contacting the lower gate electrodes and the upper gate electrodes, respectively.