Doped Polar Capacitor Stack for Low-Voltage Ferroelectric Memory
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Solution Overview
Problem
Conventional semiconductor memory technologies face challenges in achieving high remnant polarization and low coercive voltage for ultra-low voltage operation, particularly in advanced technology nodes, where maintaining nonvolatility and fast switching times is difficult.
Innovation Solution
A semiconductor device with a capacitor stack featuring a polar layer doped with a metal element from the 4d, 5d, 4f, or 5f series, integrated between crystalline conductive oxide electrodes, where the dopant concentration alters the ferroelectric switching voltage and remnant polarization, enabling low voltage switching and high remnant polarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric materials are used in capacitor, then manufacturing is simpler, but remnant polarization is insufficient for nonvolatile memory
Solution Approach 1:
The patent employs composite material structures including ferroelectric layers combined with tunnel barriers and conductive oxide electrodes. The capacitor stack integrates multiple functional layers (ferroelectric layer, tunnel barrier layer, conductive oxide electrode) to achieve high remnant polarization while maintaining compatibility with semiconductor manufacturing processes
Solution Approach 2:
The patent modifies material parameters by using ultrathin ferroelectric layers (5-50 nm thickness) and controlling doping concentrations to achieve the desired balance between high remnant polarization and low coercive voltage, enabling ultra-low voltage operation
2Quantity of substance
If higher dielectric constant is used to increase storage capacity, then leakage current increases
Solution Approach 1:
The patent uses composite dielectric structures combining ferroelectric materials with high dielectric constant and tunnel barrier materials with low leakage. The tunnel barrier layer (5-10 nm thick) effectively blocks leakage current while the ferroelectric layer provides high dielectric constant for increased storage capacity
Solution Approach 2:
The patent applies different material properties to different regions of the capacitor structure. The tunnel barrier layer provides low leakage properties at the electrode interface, while the ferroelectric layer provides high dielectric constant in the bulk, achieving local optimization of both parameters
3Area of stationary object
If device footprint is reduced for scaling, then coercive voltage increases making switching difficult
Solution Approach 1:
The patent reduces coercive voltage by using ultrathin ferroelectric layer thickness (5-50 nm) and optimizing material composition. This parameter change enables low coercive voltage operation even in scaled-down device footprints, maintaining ease of operation at advanced technology nodes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables semiconductor devices to switch at ultra-low voltages while maintaining high remnant polarization, ensuring nonvolatility and fast switching, addressing the limitations of conventional technologies in advanced nodes.
Implementation Method 1
a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV
Implementation Method 2
a polar layer comprising a base polar material doped with a dopant
Data Source
AI summary
The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a transistor formed on a silicon substrate and a capacitor electrically connected to the transistor by a conductive via. The capacitor comprises upper and lower conductive oxide electrodes on opposing sides of a polar layer, wherein the lower conductive oxide electrode is electrically connected to a drain of the transistor. The capacitor additionally comprises a polar layer comprising a base polar material doped with a dopant, wherein the base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The semiconductor device additionally comprises a lower barrier layer comprising a refractory metal or an intermetallic compound between the lower conductive oxide electrode and the conductive via.