Doped Poly-Semiconductor Gate for FinFET Threshold Control
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Solution Overview
Problem
In the manufacturing of FinFET devices, it is challenging to accurately control the distribution of doping agents in narrow gates with short channels, leading to difficulties in suppressing Short Channel Effects (SCE) and adjusting threshold voltage, especially in gate-last processes, which are costly and complex.
Innovation Solution
A method involving the formation of a doped poly-semiconductor gate stack with a gate conductive layer and insulating layer, where the poly-semiconductor is doped and annealed synchronously with source/drain regions to ensure uniform dopant distribution, improving threshold voltage accuracy and suppressing SCE at a lower cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal gate and high-k material gate stack structure are used in gate-last process, then gate controllability is improved and SCE is suppressed, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent uses a polysilicon gate as a simpler, more cost-effective alternative to the metal gate structure. The polysilicon gate can be formed using standard deposition and doping processes that are already well-established in semiconductor manufacturing, avoiding the need for complex metal gate deposition and patterning processes. This disposable-like approach uses a material and process structure that can be easily manufactured and discarded if needed, rather than requiring expensive, complex metal gate structures.
Solution Approach 2:
The patent changes the gate material parameter from metal/high-k stack to polysilicon, and adjusts the doping concentration parameters to achieve the desired threshold voltage control. By modifying the doping concentration in the polysilicon gate and the source/drain regions, the patent achieves equivalent or superior electrical characteristics without requiring the complex metal gate structure. This parameter change simplifies the manufacturing process while maintaining device performance.
2Ease of manufacture
If polysilicon gate structure is used in gate-last process with short channel, then manufacturing cost is reduced, but uniform distribution of doping agent cannot be controlled accurately
Solution Approach 1:
The patent performs preliminary doping of the polysilicon gate material before gate formation, or performs doping immediately after gate formation but before any subsequent processing that might affect the gate. By establishing the doping concentration early in the process, the patent ensures uniform distribution of the doping agent throughout the gate structure. This preliminary action prevents later variations in doping concentration that would occur if doping were delayed until after gate patterning and other processing steps.
Solution Approach 2:
The patent employs continuous doping processes or multiple doping steps with intermediate annealing to ensure uniform dopant distribution throughout the polysilicon gate. Rather than relying on a single doping step, the patent uses a continuous or multi-stage doping approach that maintains uniform concentration throughout the gate structure. This continuous useful action ensures that the doping agent is evenly distributed even in short channel devices where precision is critical.
3Ease of operation
If doping is performed separately from annealing, then process control is simplified, but dopant distribution uniformity in narrow gate deteriorates
Solution Approach 1:
The patent merges the doping and annealing steps into a single integrated process step. By combining these two operations, the patent achieves both process control simplicity and dopant distribution uniformity. The simultaneous doping and annealing ensures that dopants are introduced and immediately activated and distributed uniformly throughout the polysilicon gate, eliminating the need for separate, precisely-timed doping and annealing steps. This merged approach simplifies process control while ensuring uniform dopant distribution in narrow gate structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances the accuracy of threshold voltage adjustment and suppresses SCE in FinFET devices while reducing manufacturing costs by ensuring uniform dopant distribution in the poly-semiconductor gate.
Implementation Method 1
the poly-semiconductor layer is doped to form a doped poly-semiconductor layer
Implementation Method 2
annealing is implemented synchronously on the poly-semiconductor gate and the source/drain regions at both sides thereof so that the dopants are uniformly distributed
Implementation Method 3
depositing a gate insulating layer and a poly-semiconductor layer in turn in the gate trenches and on the top of the inter-layer dielectric layer
Data Source
AI summary
A semiconductor device is provided that has a plurality of Fin structures extending on a substrate along a first direction; a gate stack structure extending on the substrate along a second direction and across the plurality of Fin structures, wherein the gate stack structure comprises a gate conductive layer and a gate insulating layer, and the gate conductive layer is formed by a doped poly-semiconductor; trench regions in the plurality of Fin structures and beneath the gate stack structure; and source/drain regions on the plurality of Fin structures and at both sides of the gate stack structure along the first direction. A method of manufacturing a semiconductor device is also provided.