Doped Polysilicon Planarity Improvement via CMP
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits (ICs) leads to increased pattern density differences across regions, causing uneven polysilicon layers and loading effects that complicate the IC manufacturing process, particularly during chemical mechanical planarization (CMP), resulting in non-planar surfaces and uneven removal rates.
Innovation Solution
A doped polysilicon layer is introduced with a controlled dopant concentration and implantation energy to alter the removal rate of the top portion of the polysilicon layer, allowing for a planarization process that balances the removal rates across regions with varying pattern densities, ensuring a coplanar surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If polysilicon layer is deposited over regions with varying pattern densities, then the polysilicon layer covers all regions, but the upper surface becomes uneven due to loading effects
Solution Approach 1:
The patent applies local quality by introducing dopant at different concentrations in different regions of the polysilicon layer. Specifically, a first dopant concentration is introduced in a first region and a second dopant concentration is introduced in a second region, creating region-specific properties that compensate for the underlying pattern density variations and achieve uniform removal rates across the entire polysilicon layer during CMP processing
2Manufacturing precision
If CMP processing is performed on polysilicon layer with uneven upper surface, then material removal occurs, but removal rates are non-uniform across regions
Solution Approach 1:
The patent applies parameter changes by modifying the dopant concentration parameter in different regions of the polysilicon layer. By introducing a first dopant concentration in a first region and a second dopant concentration in a second region, the removal rate parameter is adjusted to compensate for pattern density variations, enabling uniform CMP processing across the entire polysilicon layer
3Manufacturing precision
If dopant concentration is increased to reduce removal rate in high pattern density regions, then removal rate imbalance is corrected, but dopant usage and process complexity increase
Solution Approach 1:
The patent implements local quality by applying different dopant concentrations to different regions of the polysilicon layer. A first dopant concentration is applied in a first region while a second dopant concentration is applied in a second region, creating spatially varying properties that enable uniform removal rates during CMP without requiring excessive dopant usage or overly complex processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The doped polysilicon layer effectively addresses the loading effect by reversing the removal rate imbalance, achieving a planar upper surface of the polysilicon layer across all regions, which is crucial for uniform gate heights and successful IC manufacturing processes.
Implementation Method 1
a doped polysilicon layer is introduced with a controlled dopant concentration and implantation energy to alter the removal rate of the top portion of the polysilicon layer
Data Source
AI summary
A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.