Doped Silicon Capping Layer for High-k Gate Stack
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Solution Overview
Problem
The integration of high-k dielectric materials with traditional polycrystalline silicon gate electrodes in semiconductor devices leads to high threshold voltage and low channel mobility, primarily due to defects at the interface, resulting in unacceptably high AC gate impedance, which affects device performance and scalability.
Innovation Solution
The implementation of a doped silicon-comprising capping layer interposed between the metal and polycrystalline silicon layers in the gate electrode stack, which can react with a silicide-forming metal capping layer to form a metal silicide, reducing interfacial defects and enhancing conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k dielectric materials are combined with traditional polycrystalline silicon gate electrodes, then gate insulation performance is improved, but threshold voltage increases and channel mobility decreases
Solution Approach 1:
A doped silicon capping layer is introduced as an intermediary between the high-k dielectric material and the polycrystalline silicon gate electrode. This intermediate layer reduces interfacial defects and improves the electrical characteristics of the gate stack, thereby resolving the contradiction between maintaining good gate insulation and avoiding threshold voltage shift and mobility degradation caused by interface defects.
2Power
If metal gate layers are added to polycrystalline silicon electrodes, then DC resistance is reduced, but AC gate impedance becomes unacceptably high
Solution Approach 1:
The doped silicon capping layer serves as a mediator between the metal gate layer and the polycrystalline silicon electrode. This layer reduces defects at the metal/polycrystalline silicon interface that cause high AC gate impedance, while allowing the metal layer to maintain its low DC resistance property, thus resolving the contradiction between DC resistance reduction and AC impedance control.
3Productivity
If critical dimensions are reduced for technology scaling, then device density is improved, but leakage current increases
Solution Approach 1:
The gate stack employs a composite structure consisting of high-k dielectric material combined with a doped silicon capping layer and metal gate layer. This composite material approach allows the use of thicker effective gate insulation to reduce leakage current while maintaining scaled dimensions, thereby enabling continued technology scaling without excessive leakage penalties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively lowers AC impedance, improves device performance by reducing defects, and enables further scalability and compatibility with high-k dielectric gate insulators, enhancing the operational frequency and drive current of transistors.
Implementation Method 1
forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer
Data Source
AI summary
Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.