Selective Etching of Doped Silicon Dioxide Tiers in 3D NAND Memory Arrays
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Solution Overview
Problem
Current methods for forming memory arrays, such as NAND architecture, face challenges in efficiently creating vertically-stacked memory cells with precise control over gate structures and charge-blocking regions, which affect the reliability and retention time of memory cells.
Innovation Solution
A 'gate-last' or 'replacement-gate' process is employed, where a stack of vertically-alternating insulative and conductive tiers is formed, with channel openings etched to create memory-block regions, and selective etching is used to divide charge-blocking and storage material strings into vertically-spaced segments, followed by the formation of conducting material to create wordlines and memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form vertically-stacked memory cells, then the manufacturing process is simpler, but the precision and reliability of gate structures and charge-blocking regions deteriorate
Solution Approach 1:
The manufacturing process is divided into distinct sequential steps: forming the stack with insulative and conductive tiers, etching channel openings, depositing charge-blocking material, forming storage material, and creating gate structures. Each step builds upon the previous one to achieve precise control over gate structures and charge-blocking regions while maintaining a manageable process complexity through systematic segmentation.
Solution Approach 2:
The stack comprising vertically-alternating insulative and conductive tiers is formed in advance before the memory cells are actually created. This preliminary formation of the stacked structure with precisely controlled layers enables subsequent precise positioning of gate structures and charge-blocking regions without requiring complex real-time adjustments during cell formation.
2Duration of action of stationary object
If vertically-stacked memory cells are formed with precise control over gate structures, then retention time improves, but manufacturing complexity increases
Solution Approach 1:
Different regions of the memory cell structure are given different materials and properties: insulative tiers for electrical isolation, conductive tiers for wordline formation, charge-blocking material for charge confinement, and storage material for data retention. This local differentiation of material properties enables precise control over gate structures and charge-blocking regions, improving retention time while keeping the overall process manageable through localized rather than global complexity.
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The second tiers comprise doped silicon dioxide and the first tiers comprise a material other than doped silicon dioxide. The stack comprises laterally-spaced memory-block regions. Channel-material-string constructions extend through the first tiers and the second tiers in the memory-block regions. The doped silicon dioxide that is in the second tiers is etched selectively relative to said other material that is in the first tiers and selectively relative to and to expose an undoped silicon dioxide-comprising string of a charge-blocking material that is part of individual of the channel-material-string constructions. Structure independent of method is disclosed.