Doped Areas Under Transistor Spacers via Sacrificial Cavities
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Solution Overview
Problem
Current MOS transistor fabrication methods face challenges in forming doped areas under spacers without overlapping the channel zone, especially at low temperatures, and inducing strain in semiconductor layers with different materials, which requires additional steps and can lead to strain relaxation.
Innovation Solution
The method involves forming sacrificial zones in the semiconductor layer on either side of the channel area, removing them to create cavities under the spacers, and filling these cavities with doped semiconductor material that can induce strain, allowing precise definition of doped areas without implantation and minimizing thermal budget.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thermal annealing is used to dope areas under spacers, then doping is achieved, but significant thermal budget is required which conflicts with low temperature fabrication methods
Solution Approach 1:
The patent replaces thermal annealing (thermal process) with ion implantation (mechanical/process substitution), where ions are directly implanted into the semiconductor layer to achieve doping without requiring high temperature thermal budget, thus resolving the contradiction between doping effectiveness and temperature constraints
Solution Approach 2:
The patent changes the doping method from thermal diffusion to ion implantation, altering the physical parameters of the doping process to achieve effective doping at lower temperatures by controlling ion energy and dosage rather than relying on thermal activation
2Temperature
If implantation is used to dope areas under spacers, then thermal budget is reduced, but additional photolithography steps are required increasing process complexity
Solution Approach 1:
The patent makes the spacer structure multi-functional by using it as both the insulating spacer and the masking layer for ion implantation, eliminating the need for separate photolithography steps. The spacer thus serves dual purposes: electrical isolation and pattern definition for doping
Solution Approach 2:
The spacer structure performs self-service by automatically serving as the mask for ion implantation without requiring additional masking layers or photolithography steps. The existing spacer geometry directly defines the doping region, making the process self-sufficient and reducing overall process complexity
3Temperature
If implantation is used for doping, then thermal budget is reduced, but strain relaxation occurs in semiconductor layers with different materials
Solution Approach 1:
The patent performs preliminary actions by forming sacrificial zones and cavities before ion implantation, creating a structured pathway that guides ion penetration and enables subsequent strain application without relaxation. The preparatory cavity formation ensures controlled doping while preserving strain in the semiconductor layer
Solution Approach 2:
The patent segments the semiconductor structure by creating cavities and removing sacrificial zones to form distinct regions. This segmentation allows selective ion implantation into specific areas while maintaining the strain structure in the channel region, preventing strain relaxation by isolating the doped areas from the strained semiconductor layer
4Reliability
If doped areas are formed to reduce resistance, then resistance between channel and source/drain is reduced, but doped areas may encroach upon the channel zone reducing precision
Solution Approach 1:
The patent introduces sacrificial zones as intermediary structures that are selectively removed to form cavities. These cavities act as intermediaries that guide the doping process, ensuring that doped areas are precisely formed under the spacers without encroaching on the channel zone, thus achieving both low resistance and high precision
Solution Approach 2:
The patent uses the vertical dimension by forming cavities that extend into the semiconductor layer and filling them with doped material. This vertical approach allows doped areas to be precisely defined under the spacers in the lateral dimension while extending vertically to reduce resistance, without encroaching on the horizontal channel zone
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of doped areas under the spacers in contact with the channel zone without overlapping, reduces the number of photolithography steps, and allows for the application of strain close to the channel, improving transistor performance.
Implementation Method 1
sacrificial zones which are achieved either side of a given area of a semi-conductor layer in which a transistor channel is to be formed
Implementation Method 2
formation of a semi-conductor material in said cavities and penetrating under the spacers, with the semi-conductor material formed in the cavities and penetrating under the spacers being doped
Data Source
AI summary
Method for fabricating a transistor comprising the steps consisting of:forming sacrificial zones in a semi-conductor layer, either side of a transistor channel zone,forming insulating spacers on said sacrificial zones against the sides of the gate of said transistor,removing said sacrificial zones so as to form cavities, with the cavities extending on either side of said channel zone and penetrating under said spacers,forming doped semi-conductor material in said cavities, with said semi-conductor material penetrating under said spacers.