Doped Interfacial Stack Structures for Void-Resistant Memory Etching
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Solution Overview
Problem
Conventional vertical memory arrays in microelectronic devices face issues such as chemical erosion and material migration during etching processes, leading to voids in dielectric materials and potential shorts between conductive structures, which can compromise the structural integrity and performance of the device.
Innovation Solution
The use of sacrificial structures with selectively etchable materials and dopant-enhanced insulative structures that maintain their shape during processing, preventing void formation and enhancing etch resistance, thereby ensuring the structural integrity and performance of the microelectronic device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used to remove sacrificial structures, then manufacturing simplicity is maintained, but chemical erosion and material migration cause voids and structural integrity issues
Solution Approach 1:
The patent applies local quality by doping only the interfacial regions of insulative structures with carbon and/or boron, while leaving central regions undoped or lightly doped. This localized doping enhances etch resistance precisely where sacrificial structures contact the insulative structures, preventing void formation without requiring complete doping of entire insulative structures, thus balancing reliability improvement with manufacturing feasibility.
Solution Approach 2:
The patent changes material parameters by introducing dopants (carbon, boron) into the insulative structure material at specific locations. This modifies the etch resistance parameter of the insulative structures at their interfaces, making them more resistant to chemical erosion and material migration during the etching process, thereby preventing voids and maintaining structural integrity.
2Reliability
If dopant concentration is increased to enhance etch resistance, then structural integrity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies that dopants are concentrated in interfacial regions with a first concentration, while central regions have a second concentration that is lower or zero. This spatial differentiation of dopant concentration allows high etch resistance where needed at interfaces without requiring uniformly high dopant concentrations throughout, thereby reducing overall manufacturing precision requirements while maintaining reliability.
Solution Approach 2:
The patent segments the insulative structures into distinct regions: doped interfacial regions and undoped or lightly-doped central regions. This segmentation allows independent optimization of each region's properties - the interfacial regions provide etch resistance where sacrificial structures contact, while central regions maintain structural integrity without requiring high dopant concentrations, thus reducing manufacturing precision demands.
3Productivity
If vertical memory array density is increased by reducing separation distances, then productivity improves, but structural stability during processing deteriorates
Solution Approach 1:
The patent applies local quality by strengthening only the interfacial regions through doping, while leaving central regions with lower dopant concentration. This localized reinforcement at interfaces provides enhanced structural support where tiers connect to insulative structures, improving tier stability during processing without requiring increased separation distances, thus allowing high memory density while maintaining stability.
Solution Approach 2:
The patent creates a composite structure within the insulative materials by combining doped interfacial regions with undoped or lightly-doped central regions. This composite approach provides enhanced mechanical and chemical properties at critical interfaces while maintaining the overall insulative function, enabling closer spacing of memory structures without compromising tier stability during processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents undesirable voiding and tier collapse, maintaining the structural integrity and performance of the microelectronic device, allowing for increased feature density and improved fabrication yields.
Implementation Method 1
The interfacial regions are doped with one or more of carbon and boron
Implementation Method 2
one or more of carbon and boron dispersed within interfacial regions of individual insulative structures
Data Source
AI summary
A microelectronic device comprises conductive structures and insulative structures vertically alternating with the conductive structures. At least one of the insulative structures includes interfacial regions extending inward from vertical boundaries of the at least one of the insulative structures, and central region vertically interposed between the interfacial regions. The interfacial regions are doped with one or more of carbon and boron. The insulative structures comprise a lower concentration of the one or more of carbon and boron than the interfacial regions. Additional microelectronic devices, electronic systems, and methods are also described.