Doped STI Structure for Ge NMOS Source/Drain Diffusion Control
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Solution Overview
Problem
Ge-rich n-MOS transistors face significant performance degradation due to n-type dopant diffusion from the source and drain regions into adjacent shallow trench isolation regions during high-temperature semiconductor fabrication, leading to high S/D contact resistance and poor conductivity.
Innovation Solution
Incorporating STI regions doped with an n-type impurity, such as phosphorous, adjacent to the source and drain regions to inhibit dopant diffusion, creating a dopant reflection effect that maintains dopant concentration and reduces diffusion gradients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-temperature fabrication processes are used, then semiconductor device formation is completed, but n-type dopant diffuses from source/drain regions into STI regions causing performance degradation
Solution Approach 1:
The STI region is pre-doped with n-type dopant before the main fabrication process. This preliminary doping creates a dopant reservoir that prevents unwanted diffusion during subsequent high-temperature processing steps, thereby maintaining transistor performance while allowing complete fabrication process execution.
Solution Approach 2:
The doped STI region acts as an intermediary between the source/drain regions and the surrounding environment. By introducing a controlled dopant concentration in the STI, it mediates the diffusion process, preventing excessive dopant migration from source/drain while allowing necessary fabrication heat treatment.
2Reliability
If dopant concentration in source/drain regions is increased, then conductivity is improved, but dopant diffusion into STI regions increases causing performance degradation
Solution Approach 1:
The patent converts the harmful effect of dopant diffusion into a beneficial outcome by pre-doping the STI region. The same diffusion mechanism that causes loss of dopant from source/drain is harnessed to maintain equilibrium dopant concentrations, as dopant naturally equilibrates between the doped STI and source/drain regions, preserving both conductivity and preventing excessive diffusion.
Solution Approach 2:
The invention changes the parameter of STI region dopant concentration from zero (undoped) to a controlled non-zero value (doped). This parameter change fundamentally alters the diffusion dynamics, creating a dopant gradient that prevents excessive dopant loss from source/drain regions while maintaining necessary conductivity.
3Ease of manufacture
If standard undoped STI regions are used, then fabrication is simpler, but dopant diffusion into STI regions causes high S/D contact resistance
Solution Approach 1:
The patent modifies the dopant concentration parameter of the STI region from standard undoped conditions to a specifically controlled doped state. This single parameter change addresses the S/D contact resistance issue by preventing dopant diffusion, while the doping process can be integrated into existing fabrication sequences, maintaining reasonable manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The doped STI regions effectively prevent dopant diffusion, enhancing Ge-rich transistor performance by maintaining dopant levels and improving S/D contact resistance, especially in sub-30 nm technology.
Implementation Method 1
n-type dopant diffusion from the source and drain regions into adjacent shallow trench isolation regions
Implementation Method 2
creating a dopant reflection effect that maintains dopant concentration and reduces diffusion gradients
Data Source
AI summary
Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the STI is doped with an n-type impurity, in regions of the STI adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the STI region is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the thickness of the doped STI region may range between 10 and 100 nanometers.