Intra-die Dose Mapper with Physical and Electrical Test Regions
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Solution Overview
Problem
Conventional wafer acceptance tests using scribe lines fail to accurately reflect the performance of intra-die integrated circuits due to non-uniformity in critical dimensions, limiting the measurement of overall die uniformity.
Innovation Solution
Intra-die integrated circuit test units, known as dose mappers (DOMAs), are designed with both physical and electrical test regions to measure critical-dimension uniformity (CDU) and saturation current uniformity (IDU) by forming a plurality of parallel conductive lines and transistors, allowing for accurate assessment of polysilicon line dimensions and transistor performance across the die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If test units are formed in scribe lines, then testing can be performed, but the test results do not accurately reflect intra-die circuit performance due to non-uniformity in critical dimensions
Solution Approach 1:
The test unit is segmented into multiple discrete test circuits distributed across the die, rather than using a single test unit in the scribe line. This segmentation allows sampling of different regions to capture intra-die variations and provides a more representative assessment of overall die uniformity.
Solution Approach 2:
The test units are distributed across the two-dimensional plane of the die rather than being confined to the one-dimensional scribe line. This spatial distribution enables measurement of critical dimensions at multiple locations, capturing the non-uniformity across the die surface and providing accurate wafer acceptance test data.
2Measurement precision
If conventional dose mappers are used, then intra-die uniformity can be measured, but various limitations reduce testing efficiency and accuracy
Solution Approach 1:
Multiple test circuits are merged into a single integrated test unit structure that can be measured together. The test unit combines multiple test circuits, each with its own active region and conductive lines, allowing simultaneous measurement of critical dimensions across different die regions, thereby improving throughput while maintaining measurement precision.
Solution Approach 2:
The test unit is designed with multi-functionality to perform various measurements including critical dimension uniformity, dose uniformity, and other process parameter assessments. This universal design allows a single test unit structure to replace multiple specialized test structures, improving productivity without sacrificing measurement capabilities.
3Measurement precision
If more test units are inserted in a die, then measurement accuracy improves, but device complexity increases
Solution Approach 1:
Each test circuit within the test unit is designed with local quality appropriate for its specific measurement function. The test circuits use identical basic structures (active region, conductive lines, contacts) but are positioned at different locations with different orientations to capture local variations in critical dimensions, achieving high measurement precision without excessive complexity.
Solution Approach 2:
The test unit varies parameters such as the orientation and positioning of conductive lines relative to active regions to measure different aspects of critical dimension uniformity. By changing these geometric parameters across multiple test circuits, the test unit can comprehensively assess intra-die uniformity while maintaining a relatively simple and scalable structure.
Data Source
AI summary
A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.