Dynamic Oxide Semiconductor RAM for Low Standby Power

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Semiconductor memory devices face high power consumption due to the volatile nature of SRAM, which loses data when powered off, and existing solutions do not effectively address reducing standby power consumption while maintaining data retention.

Innovation Solution

A semiconductor memory circuit combining SRAM with DOSRAM, utilizing oxide semiconductor field effect transistors and capacitors to transfer data from SRAM to DOSRAM, allowing SRAM to be turned off and reducing power consumption, with an additional OSFET added to block leakage current and enhance data retention accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If SRAM is used to store data, then data retention is achieved, but power consumption increases during standby

Engineering Contradiction:

Improvedata retentionVSAvoidstandby power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The memory system is divided into two segments: SRAM for active data storage and DOSRAM for standby data retention. The SRAM portion can be powered down when not in use, while only the essential DOSRAM portion remains active, segmenting the power consumption and data retention functions to resolve the contradiction between continuous power requirement and standby power savings.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention changes the operational state parameter of the SRAM from continuous operation to selective power gating. By controlling the power supply to SRAM blocks based on activity requirements, the system transitions between high-power/high-speed mode and low-power/retention mode, resolving the contradiction between power consumption and data retention.

Inventive Principle:

Principle #35Parameter changes

2Use of energy by stationary object

If SRAM is powered off to reduce power consumption, then standby power decreases, but data is lost

Engineering Contradiction:

Improvestandby power consumptionVSAvoiddata retention

Core Design Contradiction:

Use of energy by stationary objectVSReliability

Solution Approach 1:

Before powering off the SRAM to reduce standby power, the system performs a preliminary action of transferring critical data from the SRAM to the DOSRAM. This preliminary data migration ensures that essential information is preserved in the non-volatile portion before the volatile SRAM is powered down, thus maintaining data retention while enabling power savings.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The DOSRAM acts as an intermediary between the SRAM and permanent storage. When SRAM is powered down, the DOSRAM serves as a buffer that holds data temporarily, mediating the data retention requirement during the transition between powered and unpowered states, thus allowing power consumption reduction without complete data loss.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Use of energy by stationary object

If data is transferred from SRAM to DOSRAM, then power consumption is reduced, but additional circuit complexity is introduced

Engineering Contradiction:

Improvepower consumptionVSAvoidcircuit structure

Core Design Contradiction:

Use of energy by stationary objectVSDevice complexity

Solution Approach 1:

The DOSRAM circuit is designed to perform multiple functions: it serves as both the non-volatile storage medium and the transfer destination for SRAM data. The same capacitor and transistor structures in the DOSRAM are used for both long-term data retention and temporary buffering during transfer operations, reducing the need for separate dedicated transfer circuits and minimizing additional complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Measurement precision

If an additional OSFET is added to block leakage current, then data retention accuracy improves, but device complexity increases

Engineering Contradiction:

Improvedata retention accuracyVSAvoidtransistor count

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The additional OSFET is strategically placed only at critical locations where leakage current most significantly impacts data retention accuracy, rather than uniformly throughout the circuit. This localized approach blocks harmful leakage currents at their source or most problematic paths while minimizing the increase in overall device complexity by adding transistors only where absolutely necessary.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS10276578B2Dynamic oxide semiconductor random access memory(DOSRAM) having a capacitor electrically connected to the random access memory (SRAM)

Publication Date: 2019.04.30 UNITED MICROELECTRONICS CORP

AI summary

The present invention provides a semiconductor memory circuit, the semiconductor memory circuit includes a static random access memory (SRAM), having a first storage node and a second storage node, a dynamic oxide semiconductor random access memory (DOSRAM), electrically connected to the SRAM, wherein the DOSRAM includes a first oxide semiconductor field effect transistor (OSFET) and a capacitor, wherein a source of the first OSFET is electrically connected to the first storage node, and a drain of the first OSFET is electrically connected to the capacitor, and a second transistor and a third oxide semiconductor field effect transistor (OSFET), wherein a drain of the second transistor is electrically connected to the second storage node, a source of the third OSFET is electrically connected to the capacitor, and a drain of the third OSFET is electrically connected to a gate of the third transistor.