Dot Product Hardware Using Shared Partial Product Rows
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Solution Overview
Problem
Existing hardware implementations of dot product operations face challenges in reducing the number of partial product rows, which increases computational complexity, latency, and hardware area requirements.
Innovation Solution
A hardware module that groups equal weight bits of vectors into binary numbers to select partial products, reducing the number of rows needed for dot product computation by using selector circuitry and adder circuitry to perform the operation efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional hardware implementation of dot product operations is used, then computational accuracy is maintained, but the number of partial product rows increases leading to increased hardware area and computational latency
Solution Approach 1:
The patent combines multiple partial product calculations into a unified array structure where partial products from different vector element pairs are merged into shared rows. This consolidation reduces the total number of rows needed while maintaining all necessary computational relationships through selective activation and addition of merged partial products.
Solution Approach 2:
Each row in the partial product array is designed to serve multiple functions by computing partial products that can be activated for different vector element pairs. The selector circuitry enables each row to contribute to multiple dot product terms, allowing the same hardware structure to perform multiple computational roles simultaneously.
2Area of stationary object
If the number of partial product rows is reduced, then hardware area and computational delay are minimized, but the complexity of selector circuitry increases
Solution Approach 1:
The selector circuitry is divided into multiple independent selector units, each responsible for controlling a specific row in the partial product array. This segmentation allows each selector to operate independently with simplified logic, while the collective set of selectors manages the overall reduction in row count. Each selector receives control signals based on the binary encoded integers and activates appropriate partial products.
3Productivity
If binary encoded integers are used for vector elements, then computational efficiency is improved, but the complexity of grouping and selecting partial products increases
Solution Approach 1:
The vector elements are pre-encoded into binary format before entering the dot product computation pipeline. This preliminary encoding prepares the data in a form that enables efficient grouping of bits and systematic selection of partial products. The binary encoding structure is designed to align with the row organization in the partial product array, facilitating direct mapping between encoded values and row activation patterns.
Data Source
Figure 1(a)~1(b)
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AI summary
There is provided a hardware module for performing dot product operations. The hardware module comprises receiver circuitry configured to perform: receiving an input of a first vector and a second vector, each of the first and second vectors comprising at least two elements, wherein each element is a binary encoded integer. The hardware module also comprises logic circuitry configured to perform: generating an array of partial products for a dot product operation between the first vector and the second vector, the array of partial products comprising a number of, N, rows of bits. The logic circuitry comprises: grouping circuitry configured to perform: grouping bits of the at least two elements of the second vector into a binary number, wherein each binary number is associated with a respective row of the N rows of bits, and selector circuitry configured to perform: selecting a partial product value for each of the N rows of bits based on the binary number that is associated with the respective row, such that one partial product is generated per binary number. The hardware module also comprises adder circuitry configured to perform: adding the N rows of bits together to compute an output associated with the dot product operation between the first and second vectors.