Double-Bank Display Data Driving With Lock-Signal Synchronization
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Solution Overview
Problem
In organic light emitting display apparatuses with a double bank structure, asynchronous output lock signals from upper and lower data driving portions can cause a potential difference in data voltage between channels, leading to overcurrent and potential damage to data ICs.
Innovation Solution
A display apparatus with a comparison circuit that synchronizes the output lock signals from the upper and lower data driving portions, providing a synchronous lock signal to the timing control portion to adjust and stabilize the data voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a double bank structure is used with upper and lower data driving portions, then data driving capability is improved, but asynchronous output lock signals cause potential difference and overcurrent
Solution Approach 1:
The patent introduces a feedback mechanism where the comparison circuit continuously monitors the output lock signals from both upper and lower data driving portions and feeds back synchronization control signals to the timing control portion. This feedback loop ensures that any timing discrepancies are detected and corrected, preventing asynchronous operations that could cause overcurrent while maintaining the high data driving capability enabled by the double bank structure.
Solution Approach 2:
The comparison circuit serves as an intermediary component between the upper and lower data driving portions. It receives the output lock signals from both portions, compares their timing, and generates synchronization control signals that mediate the interaction between the two banks. This intermediary ensures coordinated operation and prevents direct conflicts that would lead to overcurrent, while allowing both banks to operate at full capacity.
2Ease of operation
If same lock signal is input to upper and lower data driving portions simultaneously, then operation simplicity is improved, but output lock signal timing mismatch occurs
Solution Approach 1:
The system maintains operational simplicity by inputting the same lock signal to both data driving portions while simultaneously implementing a feedback mechanism through the comparison circuit. This feedback loop monitors the output lock signals and generates synchronization control signals that compensate for timing mismatches, thus maintaining ease of operation while achieving precise timing synchronization.
Solution Approach 2:
The patent applies parameter changes by adjusting the timing control portion's operation based on the comparison results. When timing mismatches are detected, the system modifies the output timing parameters of the lock signals dynamically, ensuring synchronization without complicating the input operation. This allows the same input lock signal to produce synchronized outputs despite inherent timing variations in the double bank structure.
Data Source
AI summary
A display apparatus includes: a display panel including a plurality of data lines and a plurality of pixels; first and second data driving portions including a plurality of first and second data ICs; a timing control portion providing input first and second lock signals to the first and second data driving portions, respectively; and a comparison circuit receiving output first and second lock signals generated from the first and second data driving portions according to the input first and second lock signals, respectively, and comparing and synchronizing the output first and second lock signals to provide a synchronous lock signal to the timing control portion, wherein in a lock state of the synchronous lock signal, the timing control portion transmits image data to the first and second data driving portions, and the first and second data driving portions output respective data voltages.