Double Buffered Programmable Transport Demultiplexer Architecture

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Solution Overview

Problem

Conventional video systems struggle to efficiently process and demultiplex multiple video streams due to inflexibility and complexity, especially with the rise in different input formats and higher bit rates, leading to inadequate processing speeds and increased system costs.

Innovation Solution

A very fast programmable transport demultiplexer is developed using a double-buffered approach, combining hardware assist and firmware to handle various formats, including MPEG-2, and supporting high-speed processing of video and audio streams, with the Record Audio Video Engine (RAVE) enabling flexible algorithmic changes and high throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional systems are used to process video streams, then system simplicity is maintained, but processing speed and adaptability to different formats deteriorate

Engineering Contradiction:
Improveprocessing speedVSAvoidsystem complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The system is divided into multiple independent demultiplexer engines (first demultiplexer engine, second demultiplexer engine) that can process different video streams simultaneously. Each engine is specialized for specific tasks, allowing parallel processing and higher overall throughput while maintaining manageable complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The demultiplexer engines are designed with programmable capabilities to handle multiple video formats and standards (MPEG-2, different bit rates, various input formats) using the same hardware architecture. This universality allows the system to adapt to different formats without requiring separate dedicated hardware for each format, thus improving speed while controlling complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple different engines are used for each type of data, then adaptability to different formats is improved, but device complexity and system costs increase

Engineering Contradiction:
Improveformat adaptabilityVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system employs universal demultiplexer engines that can be programmed to handle multiple video formats and standards. Instead of having separate dedicated engines for each format, the same hardware engine can be configured through firmware to process MPEG-2, different bit rates, and various input formats, thereby achieving high adaptability without proportionally increasing hardware complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The demultiplexer engines incorporate programmable and configurable components that can be dynamically adjusted through firmware to adapt to different video formats and processing requirements. This dynamic reconfigurability allows the system to change its behavior based on the input format without requiring physical reconfiguration or multiple fixed engines

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9578139B2Method and system for architecture of a fast programmable transport demultiplexer using a double buffered approach
Publication Date: 2017.02.21 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US9578139B2 patent drawing
  • US9578139B2 patent drawing
  • US9578139B2 patent drawing

AI summary

A method and system are provided for architecture of a very fast programmable transport demultiplexer using a double-buffered approach. The method may involve utilizing a hardware assist block to process incoming packets, retrieve information about the packets, and write the retrieved information to a memory block. A firmware block may then utilize the information in memory to perform further processing on the packet data. The firmware and hardware assist blocks may work simultaneously so as to speed up the processing of the packet, which can comprise record data and/or audio/video data. The system may comprise the hardware assist block, the firmware assist block, and a memory block.