Double Buried Layer DMOS Transistor Parasitic Beta Control
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Solution Overview
Problem
Existing semiconductor manufacturing methods for DMOS transistors fail to simultaneously achieve a wide base width and high doping concentration for parasitic bipolar transistors, leading to latch-up problems and malfunctions due to the presence of parasitic PNP and NPN bipolar transistors.
Innovation Solution
The method involves forming two N-type buried layers and a P-type buried layer, along with epitaxial layers, to increase the effective base width of parasitic PNP bipolar transistors and forming a protection PNP bipolar transistor to minimize the effect of parasitic NPN bipolar transistors, thereby reducing the beta of parasitic PNP and eliminating the parasitic NPN bipolar transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single N-type buried layer is formed with wide base width, then the beta of parasitic PNP bipolar transistor is reduced, but the peak doping concentration decreases
Solution Approach 1:
The single N-type buried layer is segmented into two separate N-type buried layers (first and second N-type buried layers) with different doping concentrations. The first N-type buried layer has higher doping concentration while the second has lower doping concentration, allowing each layer to contribute differently to the overall base width and doping profile, thus reducing parasitic beta while maintaining peak doping concentration.
Solution Approach 2:
Different regions of the base are given different doping qualities through the two-layer structure. The first N-type buried layer provides high doping concentration in specific regions to maintain peak doping, while the second N-type buried layer provides extended width in other regions to reduce beta, achieving local optimization of both parameters.
2Reliability
If the base width of parasitic PNP bipolar transistor is increased, then latch-up problems are reduced, but the doping concentration must be compromised
Solution Approach 1:
The base structure is segmented into two N-type buried layers with different doping concentrations. This segmentation allows the base width to be extended (improving latch-up resistance) while the first highly-doped layer maintains the necessary doping concentration levels, decoupling the trade-off between width and concentration.
3Reliability
If parasitic NPN bipolar transistor effect is minimized by conventional methods, then device performance improves, but parasitic PNP bipolar transistor effects remain
Solution Approach 1:
A P-type buried layer is introduced as an intermediary structure between the N-type buried layers and the P-substrate. This P-type buried layer acts as a mediator that forms a protection PNP bipolar transistor, which suppresses the parasitic NPN bipolar transistor effects, while the overall double buried layer structure simultaneously addresses parasitic PNP effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes the impact of parasitic bipolar transistors by achieving a wide base width and high doping concentration without sacrificing peak doping, reducing latch-up issues and malfunctions in DMOS transistors.
Implementation Method 1
A first N-type buried layer is formed on the P-substrate. A second N-type buried layer is formed on the first N-type buried layer. A P-type buried layer is formed on a second portion of the first N-type buried layer
Implementation Method 2
A method for manufacturing double epitaxial layer N-type lateral diffusion metal oxide semiconductor transistors
Data Source
AI summary
A system and a method are disclosed for manufacturing double epitaxial layer N-type lateral diffusion metal oxide semiconductor transistors. In one embodiment two N-type buried layers are used to minimize the operation of a parasitic PNP bipolar transistor. The use of two N-type buried layers increases the base width of the parasitic PNP bipolar transistor without significantly decreasing the peak doping profiles in the two N-type buried layers. In one embodiment two N-type buried layers and one P-type buried layer are used to form a protection NPN bipolar transistor that minimizes the operation of parasitic NPN bipolar transistor. The N-type lateral diffusion metal oxide semiconductor transistors of the invention are useful in inductive full load or half bridge converter circuits that drive very high current.