Double CESL Sidewall Spacer Structure for FinFET RC Delay and TDDB
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Solution Overview
Problem
In the semiconductor industry, particularly in FinFET architecture, the conventional polysilicon gates face issues such as boron penetration and depletion, leading to reduced gate capacitance and increased time-dependent dielectric breakdown (TDDB) due to electrical field stress, which are not effectively addressed by existing technologies.
Innovation Solution
A method involving the formation of dual contact etch stop layers (CESLs) with different materials on the sidewalls of the gate structure, where a low-k material like SiOCN is used for the first CESL and a higher dielectric constant material like silicon nitride is used for the second CESL, formed through specific etching and deposition processes to address RC delay and TDDB issues simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single CESL material is used, then the structure is simple, but RC delay and TDDB cannot be effectively addressed simultaneously
Solution Approach 1:
The single CESL layer is segmented into two distinct CESL layers with different materials. The first CESL layer uses a low-k material (k<3.5) to reduce RC delay, while the second CESL layer uses a high-k material (k>3.5) to provide TDDB protection. This segmentation allows each layer to perform its specific function independently, resolving the contradiction between addressing RC delay and TDDB simultaneously.
Solution Approach 2:
The patent employs composite materials by combining two different dielectric materials with contrasting k-values in a stacked configuration. The low-k material in the first CESL layer provides excellent signal integrity by minimizing RC delay, while the high-k material in the second CESL layer provides superior electrical field management to prevent TDDB. This composite approach enables simultaneous optimization of both performance parameters.
2Speed
If low-k material is used for CESL, then RC delay is reduced, but TDDB protection is insufficient
Solution Approach 1:
The CESL structure is segmented into two functional layers: the first CESL layer with low-k material dedicated to RC delay reduction and signal propagation enhancement, and the second CESL layer with high-k material dedicated to TDDB protection. This functional segmentation allows each material to optimize its specific performance metric without compromising the other.
Solution Approach 2:
By combining low-k and high-k materials in a stacked CESL configuration, the patent creates a composite structure where the low-k layer minimizes RC delay for faster signal propagation, while the high-k layer provides strong electrical field management for TDDB protection, achieving both speed and reliability improvements simultaneously.
3Reliability
If high-k material is used for CESL, then TDDB protection is improved, but RC delay increases
Solution Approach 1:
The CESL functionality is segmented into two separate layers: the first CESL layer with low-k material handles RC delay reduction for optimal signal propagation speed, while the second CESL layer with high-k material provides TDDB protection. This segmentation eliminates the trade-off by assigning each material to its optimal function.
Solution Approach 2:
The stacked composite CESL structure combines low-k and high-k materials vertically, allowing the low-k layer to minimize RC delay and maximize signal speed, while the high-k layer simultaneously provides TDDB protection, eliminating the need to choose between speed and reliability.
4Ease of manufacture
If polysilicon gate is used, then fabrication is simple, but boron penetration and depletion effects occur
Solution Approach 1:
The gate material parameter is changed from conventional polysilicon to metal gate materials with different electrical and chemical properties. This parameter change eliminates boron penetration and depletion effects while maintaining fabrication compatibility through the dual CESL structure that manages electrical field and signaling performance.
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.