Double Control Gate Semi-Floating Transistor for Leakage Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges with high quantum tunneling effects in gate dielectric layers and weak electric field control during reading in semi-floating gate transistors, particularly at process nodes smaller than 28 nm, due to the reduced thickness of gate dielectric layers and the use of conventional control gates.
Innovation Solution
A double control gate semi-floating gate transistor structure is introduced, featuring a floating gate stack, a polysilicon control gate stack, and a metal control gate stack with a high-K dielectric layer, which includes a U-shaped groove and multiple doping types, allowing for independent operation of polysilicon and metal control gates to enhance electric field control and reduce quantum tunneling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of gate dielectric layer is reduced to less than 2 nm, then the device size can be scaled down, but the quantum tunneling effect increases and leakage current increases
Solution Approach 1:
The patent employs a composite gate structure combining SiON gate dielectric layer with HfO2 high-K dielectric material. The HfO2 layer has higher dielectric constant than SiON, allowing thicker physical thickness while maintaining equivalent electrical thickness, thus reducing quantum tunneling effect and leakage current while enabling continued device scaling.
2Object-generated harmful factors
If high-K dielectric material is used in the control gate, then the gate leakage current is reduced, but the electric field control during reading is weakened
Solution Approach 1:
The control gate is segmented into two independent gates: first control gate (CG1) with HfO2 high-K dielectric material for reducing leakage current during writing/erasing operations, and second control gate (CG2) with SiON dielectric material for providing strong electric field control during reading operations. This segmentation allows each control gate to be optimized for its specific function.
Solution Approach 2:
Different regions of the control gate structure use different dielectric materials tailored to local functional requirements. The HfO2 material is used where leakage reduction is critical (CG1), while SiON material is used where electric field control is critical (CG2). This local optimization resolves the contradiction between leakage reduction and field control.
3Device complexity
If conventional single control gate structure is used, then the device structure is simple, but the electric field control during reading is insufficient
Solution Approach 1:
The single control gate is divided into two independent control gates (CG1 and CG2) with different dielectric materials and functions. CG1 handles writing/erasing with leakage reduction, while CG2 handles reading with strong electric field control. This segmentation improves electric field control during reading while maintaining reasonable device complexity through systematic design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The double control gate structure effectively reduces quantum tunneling effects and improves power consumption by enabling better electric field control during reading and writing, allowing simultaneous reading and writing functions.
Implementation Method 1
the thickness of gate dielectric layer SiON is reduced to less than 2 nm, which leads to the increase of the leakage current of the device. The semiconductor industry uses high-K dielectric material HfO2 to replace SiON as the gate oxide layer to reduce the quantum tunneling effect of the gate dielectric layer
Implementation Method 2
The polysilicon gate can obtain better electric field control during reading and writing of the device; the polysilicon control gate and the metal control gate can work independently, such that the device achieves the function of reading and writing at the same time
Data Source
AI summary
The present application provides a double control gate semi-floating gate transistor and a method for preparing the same. A lightly doped well region provided with a U-shaped groove is located on a substrate; one part of a floating gate oxide layer covers sidewalls and a bottom of the U-shaped groove, the other part covers the lightly doped well region on one side, and the floating gate oxide layer covering the lightly doped well region; a floating gate polysilicon layer is filled in the U-shaped groove and covers the floating gate oxide layer; a polysilicon control gate stack includes a polysilicon control gate oxide layer on the floating gate polysilicon layer and a polysilicon control gate polysilicon layer on the polysilicon control gate oxide layer; a metal control gate stack includes a high-K dielectric layer and a metal gate.