Double Correlation Apparatus Using Look-Up Table
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Solution Overview
Problem
The existing double-correlation algorithm for symbol detection in direct sequence spread spectrum receivers is complex and costly in terms of silicon area, power consumption, and hardware complexity due to the large number of logic gates required for implementing the correlation function.
Innovation Solution
A correlation function apparatus comprising logic gates for multiplication and addition operations, memory units for storing multiplication values, and a sequencer for selecting chip codes, which reduces the number of logic gates and hardware complexity by performing multiplications in parallel and storing pre-calculated values for chip codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the double-correlation function is implemented using a large number of logic gates to perform all multiplication and addition operations, then the correlation calculation can be completed, but the silicon area, power consumption, and hardware complexity increase significantly
Solution Approach 1:
The patent pre-calculates and stores the products of chip code pairs (s[n]×s[n-d]) in a look-up table before the correlation operation. This preliminary action eliminates the need to perform these multiplications in real-time during the correlation function, significantly reducing the number of logic gates required while maintaining calculation accuracy.
Solution Approach 2:
The patent uses a look-up table to store pre-computed values (copies of multiplication results) that can be retrieved during the correlation operation. Instead of performing actual multiplication operations for each chip code pair, the system copies and retrieves pre-stored values, reducing hardware complexity while preserving the mathematical correctness of the correlation calculation.
2Productivity
If all multiplication operations are performed using logic gates in real-time, then the correlation function can be executed, but the power consumption increases due to the large number of active logic gates
Solution Approach 1:
The multiplication operations are performed in advance and their results are stored in the look-up table. During the actual correlation processing, only retrieval and addition operations are needed, which consume significantly less power than real-time multiplication. This separates the energy-intensive multiplication phase from the low-power execution phase.
Solution Approach 2:
Pre-computed multiplication results are copied into the look-up table and then retrieved during correlation operations. This copying approach replaces energy-intensive real-time multiplication with low-power memory access and addition operations, significantly reducing power consumption while maintaining processing speed.
3Measurement precision
If the correlation function uses a comprehensive set of logic gates to handle all chip code combinations, then the calculation is complete, but the silicon area required increases
Solution Approach 1:
All possible chip code multiplication products are pre-calculated and stored in the look-up table during manufacturing or initialization. This preliminary computation eliminates the need for physical multiplication logic gates during operation, reducing silicon area from O(N²) to O(N) where N is the number of chips per code, while preserving complete calculation coverage for all chip code combinations.
Solution Approach 2:
The look-up table stores copied values of all possible chip code products, replacing the need for physical multiplication circuits. This memory-based approach reduces silicon area by storing results rather than implementing the computational logic, while maintaining measurement precision through exact pre-computed values.
Data Source
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AI summary
An apparatus is described for performing a correlation function on a received signal and a plurality of predetermined chip codes from a communication standard. The apparatus comprising: a first plurality of logic gates configured as a multiplier unit operable to receive a signal sampled at a predetermined sampling frequency, and to perform predetermined multiplication operations on the input signal in accordance with the correlation function; a first memory unit operable to receive and store multiplication values from the first plurality of logic gates; a second memory unit having stored therein values from predetermined multiplication operations performed on the plurality of chip codes in accordance with the correlation function; and a second plurality of logic gates configured as an adder unit to receive multiplication values outputted from the first memory unit and the second memory unit and to sum the multiplication values from the first memory unit taking into account the multiplication values in the from the second memory unit.