Double Data Rate Read Capture Circuit for Skewed Timing
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Solution Overview
Problem
Existing memory interface circuits face challenges in maintaining reliable operation at high frequencies due to timing skews and interference in differential data strobe signals, particularly in mobile devices with varying clock frequencies.
Innovation Solution
A memory interface circuit with a read capture window circuit that uses a combination of differential and pseudo-differential receivers, along with a control logic block, to generate a receive clock signal that adapts to different operating states, filtering noise and ensuring timely data capture and deserialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high frequency clock signals are used to control high-speed data links, then data transmission speed is improved, but timing skew and interference increase causing unreliable operation
Solution Approach 1:
The system dynamically adjusts the receive clock signal based on detected preamble transmissions. The read capture window circuit modifies clock timing characteristics in response to actual signal conditions, enabling reliable operation across varying frequencies up to 7.2 GHz by adapting to timing skew and interference conditions rather than using fixed timing parameters
Solution Approach 2:
The patent changes the timing parameters of the receive clock signal based on detected preamble characteristics. By monitoring the differential data strobe signal and adjusting clock timing parameters accordingly, the system maintains reliable data capture despite high-frequency timing skew and interference
2Productivity
If tight timing between circuits is implemented to meet high data rates, then data transmission rate is improved, but circuit complexity increases
Solution Approach 1:
The read capture window circuit acts as an intermediary between the differential data strobe signal and the data capture circuitry. It generates a conditioned receive clock signal that simplifies the timing requirements for downstream circuits, enabling high data rates without proportionally increasing overall circuit complexity by centralizing the timing adjustment function
Solution Approach 2:
The system performs preliminary detection of preamble transmissions and generates the receive clock signal in advance of actual data capture. This preliminary timing establishment simplifies subsequent data capture operations by pre-configuring appropriate timing parameters before high-speed data transmission begins
Data Source
AI summary
A memory interface circuit includes a first receiver coupled to a differential data strobe signal and a second receiver that has a first input coupled to a reference voltage source and a second input coupled to one of the pair of complementary signals. A qualification circuit is configured to detect a preamble transmission in the differential data strobe signal based on timing provided by an output of the first receiver when the memory interface circuit is in a first operating state, detect the preamble transmission in the differential data strobe signal based on timing provided by an output of the second receiver when the memory interface circuit is in a second operating state, and assert a preamble detection signal when the preamble transmission is detected. A gating circuit is configured to provide a receive clock signal when the preamble detection signal is asserted.