Double-Deck Semiconductor Device Dual-Mold Manufacturing
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Solution Overview
Problem
Manufacturing double-deck semiconductor device packages is complex due to the need to protect one wire bonding pattern while creating another on the opposite side of the substrate, often requiring specialized leadframes and wire bonding tools, and existing methods are inefficient in integrating multiple semiconductor chips in a small package format.
Innovation Solution
A dual-mold process is employed where a first integrated circuit chip is mounted on one side of a leadframe with a wire-bonding pattern and half-molded with package molding compound, then flipped and a second chip mounted on the other side with a wire-bonding pattern using ultrasonic bonding, allowing for encapsulation of both sides with different molding compounds to protect the first die and facilitate multi-die assembly in a reliable process flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a first wire bonding pattern is provided on one side of the substrate and a second wire bonding pattern is provided on the other side, then double-deck functionality is achieved, but the first wire bonding pattern must be protected during second wire bonding operations, increasing manufacturing complexity
Solution Approach 1:
The first wire bonding pattern is protected with a protective layer before the second wire bonding operation is performed. This preliminary protective action prevents damage to the first bonding pattern during subsequent manufacturing steps, eliminating the need for complex protective measures during assembly.
Solution Approach 2:
The manufacturing process is segmented into distinct stages: first wire bonding, protective layer formation, second wire bonding, and final encapsulation. This segmentation allows each operation to be optimized independently, reducing overall manufacturing complexity while maintaining double-deck functionality.
2Reliability
If special/complex leadframes or wire bonding tools are used to manufacture double-deck packages, then reliable protection of first die is achieved, but manufacturing cost and process complexity increase
Solution Approach 1:
A temporary protective layer is applied to the first wire bonding pattern that serves its purpose during the second wire bonding operation and is then removed or integrated into the final package. This disposable protective measure is simpler and less expensive than specialized leadframes or wire bonding tools.
Solution Approach 2:
A protective layer acts as an intermediary between the first wire bonding pattern and the second wire bonding operation. This intermediary element provides the necessary protection during manufacturing without requiring complex specialized tools or leadframes.
3Adaptability or versatility
If multiple semiconductor chips are integrated in a same package to increase functionality, then performance is improved, but package manufacturing complexity and space occupation challenges increase
Solution Approach 1:
The package utilizes a double-deck three-dimensional arrangement with chips and wire bonding patterns on both sides of the substrate. This vertical stacking approach increases functionality and component density without significantly increasing the package's planar footprint, making manufacturing more manageable compared to lateral expansion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of small-outline double-deck power devices in QFP format, ensuring reliable protection of the first die during wire bonding operations and enabling efficient integration of multiple semiconductor chips, simplifying the manufacturing process and improving package dimensions.
Implementation Method 1
a second integrated circuit die is mounted on the second face of the leadframe and provided with a (second) wire-bonding pattern (aluminum wire, for instance) via an ultrasonic wire bonding technique
Data Source
AI summary
A “double-deck” semiconductor device includes a first semiconductor chip mounted to a first surface of a leadframe, with a first wire bonding pattern and a first mass of encapsulating material molded onto the first surface of the leadframe when the leadframe is in a first spatial orientation. The leadframe with the first semiconductor chip and the first wire bonding pattern encapsulated and thus protected by the first mass of encapsulating material is then turned over to a second spatial orientation. A second semiconductor chip is attached to the second surface of the leadframe, with a second wire bonding pattern and a second mass of encapsulating material, different from the first mass of encapsulating material molded onto the second surface of the leadframe.


