Double-Decked Interconnect Stack for Low-Resistance Power Routing
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Solution Overview
Problem
Integrated circuits with embedded memory face challenges in balancing ohmic resistance and capacitance requirements for different signal types, such as logic and power signals, which affects access speed and power consumption.
Innovation Solution
The implementation of a double-decked vertical stack of interconnect features with wider and taller paths for power signals to reduce resistance and narrower paths for logic signals to minimize capacitance, using selective metallization levels and varying thicknesses of barrier layers to optimize signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If wider interconnect paths are used for power signals, then resistance is reduced, but capacitance increases
Solution Approach 1:
The patent transitions from planar interconnect structures to vertical 3D stacked structures. Multiple interconnect layers are stacked vertically with via connections, allowing power signals to traverse through the vertical dimension. This dimensional change enables shorter horizontal path lengths while maintaining low resistance through increased vertical conductive cross-sections, thereby reducing both resistance and capacitance simultaneously.
Solution Approach 2:
The interconnect structure is segmented into multiple discrete layers and via connections. Power signals are routed through segmented vertical stacks rather than single long horizontal paths. This segmentation allows optimization of each segment's dimensions - wider conductors in each layer for low resistance, while the segmented nature reduces total capacitance compared to a single continuous wide conductor.
2Object-affected harmful factors
If narrower interconnect paths are used for logic signals, then capacitance is minimized, but resistance increases
Solution Approach 1:
Logic signal interconnects utilize the vertical stacking approach to reduce horizontal traversal distance. By routing signals through multiple vertical layers connected by vias, the effective path length is reduced, compensating for the narrower conductor widths. This dimensional transition maintains low capacitance while preventing resistance increase through shorter path lengths.
3Area of stationary object
If memory is embedded within the interconnect structure, then area is reduced, but signal transmission performance deteriorates
Solution Approach 1:
The patent embeds memory cells within the 3D interconnect structure by utilizing vertical stacking. Memory bit cells are formed using vertical transistor channels and capacitive structures that occupy minimal planar area. The interconnect layers are routed around and through these embedded memory structures via vertical vias, maintaining signal transmission performance by avoiding long horizontal paths through memory regions while achieving high density through vertical space utilization.
Data Source
Figure 1A~1B
Figure 1C
Figure 2
AI summary
An integrated circuit structure includes a first interconnect layer, and a second interconnect layer above the first interconnect layer. The first interconnect layer includes a first interconnect feature and a second interconnect feature. The second interconnect layer includes a third interconnect feature, a fourth interconnect feature, and a fifth interconnection feature. The third interconnect feature extends from an upper surface of the first interconnect feature to an upper surface of the second interconnect layer. In an example, the fourth interconnect feature extends from an upper surface of the second interconnect feature to below the upper surface of the second interconnect layer, and the fifth interconnect feature extends from an upper surface of the fourth interconnect feature to the upper surface of the second interconnect layer. Thus, a double-decked vertical stack of interconnect features is formed using the fourth interconnect feature within the second interconnect layer.