Double-Decked Interconnect Layout for Resistance-Capacitance Tradeoffs
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Solution Overview
Problem
Integrated circuits with embedded memory face challenges in balancing ohmic resistance and capacitance requirements for different signal types, such as logic and power signals, which affects access speed and power consumption.
Innovation Solution
The implementation of a double-decked vertical stack of interconnect features with wider lower interconnect features for power signals to reduce resistance and narrower upper interconnect features for logic signals to minimize capacitance, using selective metallization levels and varying thicknesses of barrier layers to optimize signal paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If wider interconnect features are used, then resistance is reduced, but capacitance increases
Solution Approach 1:
The interconnect structure is segmented into multiple vertical levels (first interconnect layer and second interconnect layer) with different width characteristics. The lower portion uses wider interconnect features for low resistance, while the upper portion uses narrower interconnect features for low capacitance, dividing the single interconnect path into functional segments.
Solution Approach 2:
The solution transitions from a single-plane interconnect to a three-dimensional vertical stack structure. By adding the vertical dimension with multiple interconnect layers, the design achieves both wide (low resistance) and narrow (low capacitance) characteristics at different vertical positions, resolving the contradiction through spatial dimensionality.
2Object-affected harmful factors
If narrower interconnect features are used, then capacitance is minimized, but resistance increases
Solution Approach 1:
The interconnect path is segmented vertically into different width zones. The upper interconnect layer uses narrower features to minimize capacitance for logic signals, while the lower interconnect layer compensates with wider features to maintain low resistance, dividing the electrical path into functional segments with different optimization priorities.
Solution Approach 2:
By introducing the vertical dimension through stacked interconnect layers, the design can simultaneously provide narrow upper paths (for low capacitance) and wide lower paths (for low resistance), using the third dimension to reconcile the apparent contradiction between capacitance minimization and resistance reduction.
3Device complexity
If single interconnect features are used, then structure is simple, but cannot simultaneously optimize for both power and logic signals
Solution Approach 1:
The unified interconnect structure is segmented into functionally distinct upper and lower portions with different geometric characteristics. This segmentation allows the same physical structure to serve multiple signal types optimally - the lower wide portion handles power signals requiring low resistance, while the upper narrow portion handles logic signals requiring low capacitance.
Solution Approach 2:
The vertical stack interconnect structure achieves multi-functionality by simultaneously providing optimized paths for different signal types through its three-dimensional configuration. A single physical structure serves dual purposes: the lower portion optimizes for power signal transmission while the upper portion optimizes for logic signal transmission, eliminating the need for separate interconnect structures.
Data Source
AI summary
An integrated circuit structure includes a first interconnect layer, and a second interconnect layer above the first interconnect layer. The first interconnect layer includes a first interconnect feature and a second interconnect feature. The second interconnect layer includes a third interconnect feature, a fourth interconnect feature, and a fifth interconnection feature. The third interconnect feature extends from an upper surface of the first interconnect feature to an upper surface of the second interconnect layer. In an example, the fourth interconnect feature extends from an upper surface of the second interconnect feature to below the upper surface of the second interconnect layer, and the fifth interconnect feature extends from an upper surface of the fourth interconnect feature to the upper surface of the second interconnect layer. Thus, a double-decked vertical stack of interconnect features is formed using the fourth interconnect feature within the second interconnect layer.