Double Deep Well Structure for PMOS Leakage and Thermal Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Transistors with shared substrates face issues with electrical coupling and current leakage, leading to improper function and heat dissipation problems at high operating voltages, particularly in PMOS transistors without double deep wells, which affect the reliability of semiconductor devices.
Innovation Solution
The implementation of a PMOS transistor with a double deep well structure in the substrate, including n-type and p-type dopant concentrations, and a gate structure with specific dopant concentrations and non-conductive regions to reduce serial capacitance and enhance thermal dissipation, along with a sinker well for biasing, addresses the electrical coupling and heat dissipation issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors share the same substrate, then device integration is achieved, but electrical coupling paths form between transistors causing current leakage
Solution Approach 1:
The substrate is segmented into multiple isolation regions through the formation of first and second deep wells with different dopant types. These deep wells create electrical isolation barriers that segment the continuous substrate into isolated regions, preventing unwanted current leakage paths while maintaining device integration capability
Solution Approach 2:
The deep wells act as intermediary structures between adjacent transistors. By introducing these intermediate isolation regions with specific dopant concentrations, the patent creates buffer zones that block electrical coupling between transistors while allowing them to share the same substrate
2Power
If high operating voltage is used, then switching capability is improved, but heat dissipation problems occur
Solution Approach 1:
The patent applies local quality by creating regions with different dopant concentrations and types in specific locations. The deep wells have higher dopant concentrations localized in areas where heat generation occurs, improving carrier mobility and reducing resistive heating in high-power regions while maintaining lower doping in other areas
3Reliability
If deep wells with different dopant types are formed, then substrate capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of first and second deep wells into a coordinated manufacturing process. By combining the isolation function and capacitance reduction function into a single integrated structure with complementary dopant types, the solution achieves both goals while streamlining the manufacturing process through unified well formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The double deep well structure reduces substrate capacitance and enhances thermal dissipation, improving the reliability and performance of PMOS transistors by preventing current leakage and heat-related failures.
Implementation Method 1
a first deep well in the substrate, the first deep well having a second type doping. The semiconductor device includes a second deep well in the substrate, the second deep well having the second type doping and being separated and above the first deep well
Implementation Method 2
enhance thermal dissipation
Data Source
AI summary
A semiconductor device includes a substrate having a first type doping. The semiconductor device further includes a first deep well in the substrate, the first deep well having a second type doping. The semiconductor device further includes a second deep well in the substrate, the second deep well having the second type doping and being separated and above the first deep well. The semiconductor device further includes a first well over the second deep well, the first well having the first type doping and a gate structure over the first well.