Double-Edge Clock Trigger Circuit With Matched Edge Delays
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Solution Overview
Problem
Double edge clocking techniques in electrical circuits face issues due to delays caused by inverters, leading to triggering differences between rising and falling edges, which reduce the margin for circuit triggering.
Innovation Solution
A circuit design that includes an inverter to generate inverted clock edges and pass gates with PMOS and NMOS transistors to ensure equal delays between clock edges and trigger signals, minimizing triggering differences by using parallel combinations of transistors to maintain consistent signal timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an inverter is used to generate inverted clock edges for double edge clocking, then both rising and falling edges can be used to trigger the circuit, but the inverter introduces delay that causes triggering differences between edges
Solution Approach 1:
The circuit is divided into separate paths: one path handles rising edges directly through a pass gate, while another path handles falling edges through an inverter followed by a pass gate. Each path is independently optimized to achieve equal total delay, allowing both edges to be processed with matched timing characteristics.
Solution Approach 2:
The circuit uses asymmetric configurations for the two clock edges: the rising edge path uses a direct pass gate while the falling edge path uses an inverter plus pass gate. This asymmetry in structure is compensated by adjusting control signal timing to achieve symmetric (equal) delays for both edges.
2Device complexity
If the inverter delay is not compensated, then the circuit structure remains simple, but the triggering margin is reduced due to timing differences
Solution Approach 1:
The control signal for the second pass gate is advanced in time to compensate for the inverter delay. By performing this preliminary timing adjustment, the circuit ensures that both pass gates open and close at matched times, maintaining equal delays without adding significant structural complexity.
3Manufacturing precision
If pass gates are used with controlled opening times, then equal delays can be achieved between clock edges and trigger signals, but the control mechanism becomes more complex
Solution Approach 1:
The control signals for both pass gates are generated by combining the original clock signal with its inverted version through logical operations. This merging approach allows both pass gates to be controlled with a unified control mechanism that ensures equal delays without requiring separate complex control circuits.
Data Source
AI summary
A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit including an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; a first pass gate for receiving the inverted clock edge and outputting a first trigger signal of a first polarity; and a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal.