Double-Edge D Flip-Flop With Conditional Pulse Generation
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Solution Overview
Problem
Conventional D flip-flops face challenges in achieving high speed and low power consumption due to complex circuit structures and high power consumption associated with redundant narrow pulse signals, which affect the performance of digital systems in VLSI design.
Innovation Solution
A D flip-flop design incorporating a pulse signal generating circuit and latching circuit that responds to both rising and falling edges of a clock signal, with a clock pulse signal generated only when the data signal differs from the previous state, reducing redundant pulse generation and power consumption by keeping the clock pulse signal at a low level when signals are the same.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional master-slave flip-flops are used, then the circuit structure is relatively complex, but the speed is limited due to positive setup time
Solution Approach 1:
The flip-flop is divided into two independent modules: a pulse generating circuit that produces narrow pulses on clock edges, and a latch circuit that performs data sampling. This segmentation allows each module to be optimized independently, reducing overall complexity while enabling negative setup time operation
Solution Approach 2:
The pulse generating circuit uses periodic clock signals to trigger narrow pulse generation at rising and falling edges. This periodic action enables the latch circuit to sample data at specific intervals, achieving double-edge triggering with reduced setup time requirements
2Adaptability or versatility
If parallel-connected single-edge master-slave flip-flops are used, then double-edge triggering is achieved, but power consumption is relatively large
Solution Approach 1:
Two single-edge flip-flops are merged into a single integrated structure where the pulse generating circuit shares common components for both rising and falling edge detection. The latch circuit is simultaneously controlled by both edges, reducing redundant circuitry and lowering power consumption while maintaining double-edge functionality
Solution Approach 2:
The circuit discards redundant pulse generation when the data signal does not change between clock edges. The pulse generating circuit detects data stability and suppresses unnecessary narrow pulse output, recovering power that would otherwise be consumed by redundant switching operations in the latch circuit
3Loss of time
If pulse double-edge D flip-flops are used, then negative setup time is achieved, but redundant narrow signals increase power consumption
Solution Approach 1:
The pulse generating circuit incorporates feedback from the data signal to control pulse generation. When the data signal remains unchanged between clock edges, the feedback mechanism suppresses redundant narrow pulse output, thereby reducing unnecessary power consumption in the latch circuit while maintaining negative setup time capability
Solution Approach 2:
The circuit dynamically adjusts pulse generation based on data signal changes. The pulse generating circuit transitions between active pulse generation and suppression modes according to data stability, optimizing the balance between setup time performance and power consumption in real-time operation
Data Source
Figure 1
Figure 2(a)~2(b)
Figure 3~4
AI summary
The present invention provides D flip-flops (100) and signal driving methods (fig. 8) using D flip-flops thereof. An exemplary D flip-flop includes a pulse signal generating circuit (10) configured to input a first clock signal (CP), a first data signal (D), a second data signal (Q) and a third data signal (Qb) and generate a clock pulse signal (CP_Pulse). The clock pulse signal (CP_Pulse) responds a raising-edge and a falling-edge of the first clock signal (CP). The pulse clock signal (CP_Pulse) is a pulse signal when the first data signal (D) is opposite to the second data signal (Q). The D flip-flop also includes a latching circuit (20) configured to sample and transfer the first data signal (D) and a data signal opposite to the first data signal (Db) to be used as the second signal (Q) and a fourth data (third data Qb) signal respectively when the clock signal (CP_Pulse) is at the high level.