Double Embedded Interposer Substrate Via Design
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Solution Overview
Problem
Current semiconductor device packages face challenges in meeting the requirements of both high and low density interconnect pitches, leading to difficulties in designing and testing, as well as high manufacturing costs and low yield, particularly due to the complexity of manufacturing fine pitch interposer substrates and the risk of cracking during via formation.
Innovation Solution
A double embedded patterned interposer substrate with a middle patterned conductive layer buried between two dielectric layers, featuring conductive vias with varying widths to connect circuit patterns, which reduces the risk of cracking and allows for a transition between high and low density interconnect pitches, and a manufacturing method that includes forming vias and metal plating to align with the middle patterned conductive layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine pitch interconnect patterns are implemented to accommodate large numbers of input/output signals, then the number of input/output signals increases, but the manufacturing complexity and cost increase significantly
Solution Approach 1:
The interposer substrate is divided into multiple layers with different interconnect pitch densities. High density interconnect patterns are implemented in certain layers to accommodate large numbers of I/O signals, while low density patterns are used in other layers for connections to the system substrate. This segmentation allows each layer to be optimized for its specific function, reducing overall manufacturing complexity while maintaining high signal capacity.
2Quantity of substance
If high density interconnect pitch is implemented in the base substrate to connect semiconductor devices, then the signal transmission capacity increases, but it becomes difficult to also implement lower density interconnect pitch for system substrate connections
Solution Approach 1:
The patent utilizes the vertical dimension by implementing multiple layers of interconnect patterns with different pitch densities. High density patterns are placed in layers closer to the semiconductor device side, while low density patterns are placed in layers closer to the system substrate side. This multi-layer approach allows the base substrate to simultaneously provide both high density connections for device I/O signals and low density connections for system substrate interfacing.
3Reliability
If via holes are formed during manufacturing to connect circuit patterns, then electrical connectivity is achieved, but cracking may occur during the via formation process
Solution Approach 1:
The patent forms via holes and fills them with conductive material in advance, before subsequent manufacturing steps that may cause stress or cracking. By completing the via formation process early in the manufacturing sequence, the structural integrity of the substrate is preserved during later processing steps, reducing the risk of cracking while ensuring electrical connectivity is established.
Data Source
AI summary
An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.